Guide on implementing on the fpga #2
Description
Hello! Nice work on your project and i'm interested in recreating your work for a student club! I'm new to FPGA and currently using a Xilinx Artix-7 FPGA (Nexys 4 ddr) with Vivado. May I know if i should include all the verilog files from your src1 and src2 folders into VIvado? Could you provide a step-by-step guide on how you implemented this on your fpga? And how did you connect your camera module? Thanks so much!