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author
Stepan Friedl
committed
Merge branch 'xkosar02-ftile-set-vsr-mode' into 'devel'
feat(network-mod): add support for setting F-TILE VSR mode via generic See merge request ndk/ndk-fpga!346
2 parents ef2cee4 + 6eea146 commit 757ebb0

18 files changed

Lines changed: 174 additions & 28 deletions

‎cards/bittware/ia-860m/src/fpga_2ports.vhd‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,8 @@ architecture FULL of FPGA is
9696
constant DMA_ENDPOINTS : integer := tsel(DMA_TYPE=3, 4, 1);
9797
constant QSFP_PORTS : natural := 2;
9898
constant DEVICE : string := "AGILEX";
99+
-- VSR mode 00 (low loss) doesn't work for IA-860m. Therefore, mode 10 (VSR disabled) must be used.
100+
constant VSR_MODE_SEL : std_logic_vector(1 downto 0) := "10";
99101

100102
--Ethernet
101103
signal eth_rx_p : std_logic_vector(ETH_PORTS*ETH_LANES-1 downto 0);
@@ -157,6 +159,7 @@ begin
157159
ETH_PORT_CHAN => ETH_PORT_CHAN,
158160
ETH_PORT_LEDS => 1,
159161
ETH_LANES => ETH_LANES,
162+
FTILE_VSR_MODE_SEL => VSR_MODE_SEL,
160163

161164
QSFP_PORTS => QSFP_PORTS,
162165
QSFP_I2C_PORTS => QSFP_PORTS,

‎cards/bittware/ia-860m/src/fpga_3ports.vhd‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -104,6 +104,8 @@ architecture FULL of FPGA is
104104
constant DMA_ENDPOINTS : integer := tsel(DMA_TYPE=3, 4, 1);
105105
constant QSFP_PORTS : natural := 3;
106106
constant DEVICE : string := "AGILEX";
107+
-- VSR mode 00 (low loss) doesn't work for IA-860m. Therefore, mode 10 (VSR disabled) must be used.
108+
constant VSR_MODE_SEL : std_logic_vector(1 downto 0) := "10";
107109

108110
--Ethernet
109111
signal eth_rx_p : std_logic_vector(ETH_PORTS*ETH_LANES-1 downto 0);
@@ -167,6 +169,7 @@ begin
167169
ETH_PORT_CHAN => ETH_PORT_CHAN,
168170
ETH_PORT_LEDS => 1,
169171
ETH_LANES => ETH_LANES,
172+
FTILE_VSR_MODE_SEL => VSR_MODE_SEL,
170173

171174
QSFP_PORTS => QSFP_PORTS,
172175
QSFP_I2C_PORTS => QSFP_PORTS,

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_1x400g8.vhd‎

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,15 @@ use work.math_pack.all;
1010
use work.type_pack.all;
1111

1212
entity FTILE_1X400G8 is
13+
generic (
14+
-- ===================================================================
15+
-- Select VSR mode for F-Tile. Values:
16+
-- - 00 means optical mode configuration (LR/SR)
17+
-- - 01 means CR mode configuration
18+
-- - 10 is for cards for which 00 doesn't work due to high loss
19+
-- ===================================================================
20+
VSR_MODE_SEL : std_logic_vector(1 downto 0)
21+
);
1322
port (
1423
-- ===================================================================
1524
-- MGMT Interface
@@ -503,7 +512,7 @@ begin
503512
RST => RESET_ETH or mgmt_pma_reset,
504513
XCVR_RDY => init_ready(xcvr),
505514
CLK => MI_CLK_PHY,
506-
ROM_SEL => "0", -- 0 means optical mode configuration, 1 means CR mode configuration
515+
ROM_SEL => VSR_MODE_SEL, -- 00 means optical mode configuration, 01 means CR mode configuration, 10 is for cards for which 00 doesn't work
507516
BUSY => init_busy,
508517
DONE => init_done(xcvr),
509518
-- AVMM
@@ -514,7 +523,7 @@ begin
514523
READDATA_VALID => reconfig_readdata_valid(IA_INDEX),
515524
WRITEDATA => init_writedata,
516525
WAITREQUEST => reconfig_waitrequest(IA_INDEX),
517-
STATE => open -- debug purposes only. Can be left open in the future
526+
STATE => open -- debug purposes only. Can be left open in the future
518527
);
519528

520529
end generate;

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x100g4.vhd‎

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,15 @@ use work.math_pack.all;
1010
use work.type_pack.all;
1111

1212
entity FTILE_2X100G4 is
13+
generic (
14+
-- ===================================================================
15+
-- Select VSR mode for F-Tile. Values:
16+
-- - 00 means optical mode configuration (LR/SR)
17+
-- - 01 means CR mode configuration
18+
-- - 10 is for cards for which 00 doesn't work due to high loss
19+
-- ===================================================================
20+
VSR_MODE_SEL : std_logic_vector(1 downto 0)
21+
);
1322
port (
1423
-- ===================================================================
1524
-- MGMT Interface
@@ -474,7 +483,7 @@ begin
474483
RST => RESET_ETH or mgmt_pma_reset,
475484
XCVR_RDY => init_ready(xcvr),
476485
CLK => MI_CLK_PHY,
477-
ROM_SEL => "0", -- 0 means optical mode configuration, 1 means CR mode configuration
486+
ROM_SEL => VSR_MODE_SEL, -- 00 means optical mode configuration, 01 means CR mode configuration, 10 is for cards for which 00 doesn't work
478487
BUSY => init_busy,
479488
DONE => init_done(xcvr),
480489
-- AVMM
@@ -485,7 +494,7 @@ begin
485494
READDATA_VALID => reconfig_readdata_valid(IA_INDEX),
486495
WRITEDATA => init_writedata,
487496
WAITREQUEST => reconfig_waitrequest(IA_INDEX),
488-
STATE => open -- debug purposes only. Can be left open in the future
497+
STATE => open -- debug purposes only. Can be left open in the future
489498
);
490499

491500
end generate;

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x200g4.vhd‎

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,15 @@ use work.math_pack.all;
1010
use work.type_pack.all;
1111

1212
entity FTILE_2X200G4 is
13+
generic (
14+
-- ===================================================================
15+
-- Select VSR mode for F-Tile. Values:
16+
-- - 00 means optical mode configuration (LR/SR)
17+
-- - 01 means CR mode configuration
18+
-- - 10 is for cards for which 00 doesn't work due to high loss
19+
-- ===================================================================
20+
VSR_MODE_SEL : std_logic_vector(1 downto 0)
21+
);
1322
port (
1423
-- ===================================================================
1524
-- MGMT Interface
@@ -471,7 +480,7 @@ begin
471480
RST => RESET_ETH or mgmt_pma_reset,
472481
XCVR_RDY => init_ready(xcvr),
473482
CLK => MI_CLK_PHY,
474-
ROM_SEL => "0", -- 0 means optical mode configuration, 1 means CR mode configuration
483+
ROM_SEL => VSR_MODE_SEL, -- 00 means optical mode configuration, 01 means CR mode configuration, 10 is for cards for which 00 doesn't work
475484
BUSY => init_busy,
476485
DONE => init_done(xcvr),
477486
-- AVMM
@@ -482,7 +491,7 @@ begin
482491
READDATA_VALID => reconfig_readdata_valid(IA_INDEX),
483492
WRITEDATA => init_writedata,
484493
WAITREQUEST => reconfig_waitrequest(IA_INDEX),
485-
STATE => open -- debug purposes only. Can be left open in the future
494+
STATE => open -- debug purposes only. Can be left open in the future
486495
);
487496

488497
end generate;

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x40g4.vhd‎

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,15 @@ use work.math_pack.all;
1010
use work.type_pack.all;
1111

1212
entity FTILE_2X40G4 is
13+
generic (
14+
-- ===================================================================
15+
-- Select VSR mode for F-Tile. Values:
16+
-- - 00 means optical mode configuration (LR/SR)
17+
-- - 01 means CR mode configuration
18+
-- - 10 is for cards for which 00 doesn't work due to high loss
19+
-- ===================================================================
20+
VSR_MODE_SEL : std_logic_vector(1 downto 0)
21+
);
1322
port (
1423
-- ===================================================================
1524
-- MGMT Interface
@@ -472,7 +481,7 @@ begin
472481
RST => RESET_ETH or mgmt_pma_reset,
473482
XCVR_RDY => init_ready(xcvr),
474483
CLK => MI_CLK_PHY,
475-
ROM_SEL => "0", -- 0 means optical mode configuration, 1 means CR mode configuration
484+
ROM_SEL => VSR_MODE_SEL, -- 00 means optical mode configuration, 01 means CR mode configuration, 10 is for cards for which 00 doesn't work
476485
BUSY => init_busy,
477486
DONE => init_done(xcvr),
478487
-- AVMM
@@ -483,7 +492,7 @@ begin
483492
READDATA_VALID => reconfig_readdata_valid(IA_INDEX),
484493
WRITEDATA => init_writedata,
485494
WAITREQUEST => reconfig_waitrequest(IA_INDEX),
486-
STATE => open -- debug purposes only. Can be left open in the future
495+
STATE => open -- debug purposes only. Can be left open in the future
487496
);
488497

489498
end generate;

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_4x100g2.vhd‎

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,15 @@ use work.math_pack.all;
1010
use work.type_pack.all;
1111

1212
entity FTILE_4X100G2 is
13+
generic (
14+
-- ===================================================================
15+
-- Select VSR mode for F-Tile. Values:
16+
-- - 00 means optical mode configuration (LR/SR)
17+
-- - 01 means CR mode configuration
18+
-- - 10 is for cards for which 00 doesn't work due to high loss
19+
-- ===================================================================
20+
VSR_MODE_SEL : std_logic_vector(1 downto 0)
21+
);
1322
port (
1423
-- ===================================================================
1524
-- MGMT Interface
@@ -455,7 +464,7 @@ begin
455464
RST => RESET_ETH or mgmt_pma_reset,
456465
XCVR_RDY => init_ready(xcvr),
457466
CLK => MI_CLK_PHY,
458-
ROM_SEL => "0", -- 0 means optical mode configuration, 1 means CR mode configuration
467+
ROM_SEL => VSR_MODE_SEL, -- 00 means optical mode configuration, 01 means CR mode configuration, 10 is for cards for which 00 doesn't work
459468
BUSY => init_busy,
460469
DONE => init_done(xcvr),
461470
-- AVMM
@@ -466,7 +475,7 @@ begin
466475
READDATA_VALID => reconfig_readdata_valid(IA_INDEX),
467476
WRITEDATA => init_writedata,
468477
WAITREQUEST => reconfig_waitrequest(IA_INDEX),
469-
STATE => open -- debug purposes only. Can be left open in the future
478+
STATE => open -- debug purposes only. Can be left open in the future
470479
);
471480

472481
end generate;

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_8x10g1.vhd‎

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,15 @@ use work.math_pack.all;
1010
use work.type_pack.all;
1111

1212
entity FTILE_8X10G1 is
13+
generic (
14+
-- ===================================================================
15+
-- Select VSR mode for F-Tile. Values:
16+
-- - 00 means optical mode configuration (LR/SR)
17+
-- - 01 means CR mode configuration
18+
-- - 10 is for cards for which 00 doesn't work due to high loss
19+
-- ===================================================================
20+
VSR_MODE_SEL : std_logic_vector(1 downto 0)
21+
);
1322
port (
1423
-- ===================================================================
1524
-- MGMT Interface
@@ -444,7 +453,7 @@ begin
444453
RST => RESET_ETH or mgmt_pma_reset,
445454
XCVR_RDY => init_ready(xcvr),
446455
CLK => MI_CLK_PHY,
447-
ROM_SEL => "0", -- 0 means optical mode configuration, 1 means CR mode configuration
456+
ROM_SEL => VSR_MODE_SEL, -- 00 means optical mode configuration, 01 means CR mode configuration, 10 is for cards for which 00 doesn't work
448457
BUSY => init_busy,
449458
DONE => init_done(xcvr),
450459
-- AVMM
@@ -455,7 +464,7 @@ begin
455464
READDATA_VALID => reconfig_readdata_valid(IA_INDEX),
456465
WRITEDATA => init_writedata,
457466
WAITREQUEST => reconfig_waitrequest(IA_INDEX),
458-
STATE => open -- debug purposes only. Can be left open in the future
467+
STATE => open -- debug purposes only. Can be left open in the future
459468
);
460469
end generate;
461470

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_8x25g1.vhd‎

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,15 @@ use work.math_pack.all;
1010
use work.type_pack.all;
1111

1212
entity FTILE_8X25G1 is
13+
generic (
14+
-- ===================================================================
15+
-- Select VSR mode for F-Tile. Values:
16+
-- - 00 means optical mode configuration (LR/SR)
17+
-- - 01 means CR mode configuration
18+
-- - 10 is for cards for which 00 doesn't work due to high loss
19+
-- ===================================================================
20+
VSR_MODE_SEL : std_logic_vector(1 downto 0)
21+
);
1322
port (
1423
-- ===================================================================
1524
-- MGMT Interface
@@ -447,7 +456,7 @@ begin
447456
RST => RESET_ETH or mgmt_pma_reset,
448457
XCVR_RDY => init_ready(xcvr),
449458
CLK => MI_CLK_PHY,
450-
ROM_SEL => "0", -- 0 means optical mode configuration, 1 means CR mode configuration
459+
ROM_SEL => VSR_MODE_SEL, -- 00 means optical mode configuration, 01 means CR mode configuration, 10 is for cards for which 00 doesn't work
451460
BUSY => init_busy,
452461
DONE => init_done(xcvr),
453462
-- AVMM
@@ -458,7 +467,7 @@ begin
458467
READDATA_VALID => reconfig_readdata_valid(IA_INDEX),
459468
WRITEDATA => init_writedata,
460469
WAITREQUEST => reconfig_waitrequest(IA_INDEX),
461-
STATE => open -- debug purposes only. Can be left open in the future
470+
STATE => open -- debug purposes only. Can be left open in the future
462471
);
463472
end generate;
464473

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_8x50g1.vhd‎

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,15 @@ use work.math_pack.all;
1010
use work.type_pack.all;
1111

1212
entity FTILE_8X50G1 is
13+
generic (
14+
-- ===================================================================
15+
-- Select VSR mode for F-Tile. Values:
16+
-- - 00 means optical mode configuration (LR/SR)
17+
-- - 01 means CR mode configuration
18+
-- - 10 is for cards for which 00 doesn't work due to high loss
19+
-- ===================================================================
20+
VSR_MODE_SEL : std_logic_vector(1 downto 0)
21+
);
1322
port (
1423
-- ===================================================================
1524
-- MGMT Interface
@@ -447,7 +456,7 @@ begin
447456
RST => RESET_ETH or mgmt_pma_reset,
448457
XCVR_RDY => init_ready(xcvr),
449458
CLK => MI_CLK_PHY,
450-
ROM_SEL => "0", -- 0 means optical mode configuration, 1 means CR mode configuration
459+
ROM_SEL => VSR_MODE_SEL, -- 00 means optical mode configuration, 01 means CR mode configuration, 10 is for cards for which 00 doesn't work
451460
BUSY => init_busy,
452461
DONE => init_done(xcvr),
453462
-- AVMM
@@ -458,7 +467,7 @@ begin
458467
READDATA_VALID => reconfig_readdata_valid(IA_INDEX),
459468
WRITEDATA => init_writedata,
460469
WAITREQUEST => reconfig_waitrequest(IA_INDEX),
461-
STATE => open -- debug purposes only. Can be left open in the future
470+
STATE => open -- debug purposes only. Can be left open in the future
462471
);
463472

464473
end generate;

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