Merge branch 'kondys_axi_concatenator' into 'devel'

feat(axis_tools): introduce AXIS_PACKET_CONCATENATOR, a component to merge two frames into one

See merge request ndk/ndk-fpga!378

Author: jakubcabal

comp/axis_tools/edit/packet_concatenator/Modules.tcl

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+# Modules.tcl: Components include script
+# Copyright (C) 2026 CESNET
+# Author(s): Daniel Kondys <kondys@cesnet.cz>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Component paths
+set PKG_BASE            "$OFM_PATH/comp/base/pkg"
+set LOGIC_BASE          "$OFM_PATH/comp/base/logic"
+
+# Packages
+lappend PACKAGES "$PKG_BASE/math_pack.vhd"
+lappend PACKAGES "$PKG_BASE/type_pack.vhd"
+
+# Components
+lappend COMPONENTS [ list "LAST_ONE"           "$LOGIC_BASE/last_one"       "FULL" ]
+lappend COMPONENTS [ list "BARREL_SHIFTER_GEN" "$LOGIC_BASE/barrel_shifter" "FULL" ]
+lappend COMPONENTS [ list "GEN_ENC"            "$LOGIC_BASE/enc"            "FULL" ]
+
+# Files
+lappend MOD "$ENTITY_BASE/axis_packet_concatenator.vhd"

comp/axis_tools/edit/packet_concatenator/axis_packet_concatenator.vhd

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+# Makefile: Makefile to compile module
+# Copyright (C) 2026 CESNET z. s. p. o.
+# Author(s): Daniel Kondys <kondys@cesnet.cz>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+TOP_LEVEL_ENT=AXIS_PACKET_CONCATENATOR
+TARGET=cocotb
+
+.PHONY: all
+all: comp
+
+include ../../../../../build/Makefile

comp/axis_tools/edit/packet_concatenator/cocotb/Makefile

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+# Copyright (C) 2026 CESNET z. s. p. o.
+# Author(s): Daniel Kondys <kondys@cesnet.cz>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+import itertools
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import ClockCycles
+
+from cocotbext.ofm.axi4stream.transaction import Axi4StreamTransaction
+from cocotbext.ofm.base.generators import ItemRateLimiter
+from cocotbext.ofm.ver.generators import random_transactions
+
+from testbench import Testbench
+
+
+@cocotb.test()
+async def run_base_test(dut, min_size=40, max_size=200, pkt_count=10000):
+    """Base test with random gaps and backpressure, random packet sizes min_size-max_size."""
+    cocotb.log.info("Starting AXIS_PACKET_CONCATENATOR base test")
+
+    # Start clock generator
+    cocotb.start_soon(Clock(dut.CLK, 5, units="ns").start())
+
+    tb = Testbench(dut, debug=False)
+
+    # Set up rate limiters for both input streams
+    idle_gen_conf = dict(random_idles=True, max_idles=5, zero_idles_chance=50)
+    tb.rx0_drv.set_idle_generator(ItemRateLimiter(rate_percentage=20, **idle_gen_conf))
+    tb.rx1_drv.set_idle_generator(ItemRateLimiter(rate_percentage=90, **idle_gen_conf))
+
+    await tb.reset()
+
+    # Start backpressure
+    tb.backpressure.start((1, i % 3) for i in itertools.count())
+
+    # Generate and send transactions using random_transactions generator
+    rx0_gen = random_transactions(Axi4StreamTransaction, tb.rx0_drv, "TDATA", min_size, max_size, pkt_count)
+    rx1_gen = random_transactions(Axi4StreamTransaction, tb.rx1_drv, "TDATA", 20, 70, pkt_count)
+
+    for i, (rx0_tr, rx1_tr) in enumerate(zip(rx0_gen, rx1_gen)):
+        cocotb.log.debug(f"Generated packets iteration #{i}: RX0={len(rx0_tr.TDATA)}B, RX1={len(rx1_tr.TDATA)}B")
+
+        # Model the expected output
+        tb.model(rx0_tr, rx1_tr)
+
+        # Send to DUT
+        tb.rx0_drv.append(rx0_tr)
+        tb.rx1_drv.append(rx1_tr)
+
+    await ClockCycles(dut.CLK, 10)
+
+    # Wait for all transactions to be received
+    last_num = 0
+    while tb.tx_mon.frame_cnt < pkt_count:
+        if (tb.tx_mon.frame_cnt // 1000) > last_num:
+            last_num = tb.tx_mon.frame_cnt // 1000
+            cocotb.log.info(f"Number of transactions processed: {tb.tx_mon.frame_cnt}/{pkt_count}")
+        await ClockCycles(dut.CLK, 100)
+
+    cocotb.log.info(f"Test completed: {tb.tx_mon.frame_cnt}/{pkt_count} packets processed")
+    raise tb.scoreboard.result
+
+
+@cocotb.test()
+async def run_full_speed_test(dut, min_size=40, max_size=500, pkt_count=10000):
+    """Full speed test without gaps and backpressure, random packet sizes min_size-max_size."""
+    cocotb.log.info("Starting AXIS_PACKET_CONCATENATOR full speed test")
+
+    # Start clock generator
+    cocotb.start_soon(Clock(dut.CLK, 5, units="ns").start())
+
+    tb = Testbench(dut, debug=False)
+
+    # No idle generators - full speed on input
+    # No backpressure - full speed on output
+    dut.TX_AXIS_TREADY.value = 1
+
+    await tb.reset()
+
+    # Generate and send transactions using random_transactions generator
+    rx0_gen = random_transactions(Axi4StreamTransaction, tb.rx0_drv, "TDATA", min_size, max_size, pkt_count)
+    rx1_gen = random_transactions(Axi4StreamTransaction, tb.rx1_drv, "TDATA", 1, 20, pkt_count)
+
+    for i, (rx0_tr, rx1_tr) in enumerate(zip(rx0_gen, rx1_gen)):
+        cocotb.log.debug(f"Generated packets iteration #{i}: RX0={len(rx0_tr.TDATA)}B, RX1={len(rx1_tr.TDATA)}B")
+
+        # Model the expected output
+        tb.model(rx0_tr, rx1_tr)
+
+        # Send to DUT
+        tb.rx0_drv.append(rx0_tr)
+        tb.rx1_drv.append(rx1_tr)
+
+    await ClockCycles(dut.CLK, 10)
+
+    # Wait for all transactions to be received
+    last_num = 0
+    while tb.tx_mon.frame_cnt < pkt_count:
+        if (tb.tx_mon.frame_cnt // 1000) > last_num:
+            last_num = tb.tx_mon.frame_cnt // 1000
+            cocotb.log.info(f"Number of transactions processed: {tb.tx_mon.frame_cnt}/{pkt_count}")
+        await ClockCycles(dut.CLK, 100)
+
+    cocotb.log.info(f"Test completed: {tb.tx_mon.frame_cnt}/{pkt_count} packets processed")
+    raise tb.scoreboard.result

comp/axis_tools/edit/packet_concatenator/cocotb/cocotb_test.py

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+# cocotb_test_sig.fdo : Include file with signals
+# Copyright (C) 2026 CESNET z. s. p. o.
+# Author(s): Daniel Kondys <kondys@cesnet.cz>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+view wave
+delete wave *
+
+add_wave -group {Top} -noupdate -hex /axis_frame_concatenator/*
+
+config wave -signalnamewidth 1

comp/axis_tools/edit/packet_concatenator/cocotb/cocotb_test_sig.fdo

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+[project]
+name = "cocotb-packet-concatenator"
+version = "0.1.0"
+dependencies = [
+    "cocotbext-ofm[nfb] @ ${NDK_FPGA_COCOTBEXT_OFM_URL}",
+    "setuptools",
+]
+
+[build-system]
+requires = ["pdm-backend"]
+build-backend = "pdm.backend"

comp/axis_tools/edit/packet_concatenator/cocotb/pyproject.toml

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+# Copyright (C) 2026 CESNET z. s. p. o.
+# Author(s): Daniel Kondys <kondys@cesnet.cz>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+"""Testbench for AXIS_PACKET_CONCATENATOR component."""
+
+import cocotb
+from cocotb.triggers import RisingEdge, ClockCycles
+from cocotb_bus.drivers import BitDriver
+from cocotb_bus.scoreboard import Scoreboard
+
+from cocotbext.ofm.axi4stream.drivers import Axi4StreamMaster
+from cocotbext.ofm.axi4stream.monitors import Axi4Stream
+from cocotbext.ofm.axi4stream.transaction import Axi4StreamTransaction
+
+
+def _format_bytes(data: bytes, bytes_per_line: int = 32) -> str:
+    """Format bytes as a readable string with hex values separated by spaces.
+
+    Args:
+        data: The bytes data to format.
+        bytes_per_line: Number of bytes to display per line.
+
+    Returns:
+        A formatted string with hex values separated by spaces.
+    """
+    if not isinstance(data, bytes):
+        return str(data)
+
+    lines = []
+    for i in range(0, len(data), bytes_per_line):
+        chunk = data[i:i + bytes_per_line]
+        # Format each byte as two-digit hex with space separator
+        hex_bytes = ' '.join(f'{b:02x}' for b in chunk)
+        # Add offset at the beginning of each line
+        lines.append(f"  0x{i:04x}: {hex_bytes}")
+
+    return '\n'.join(lines) if lines else "  (empty)"
+
+
+def _format_transaction(transaction, label: str) -> str:
+    """Format a transaction for display.
+
+    Args:
+        transaction: The transaction to format (expected or received).
+        label: Label to display (e.g., "MODEL" or "DUT").
+
+    Returns:
+        A formatted string representation of the transaction.
+    """
+    # Get TDATA from transaction
+    if hasattr(transaction, 'TDATA'):
+        data = transaction.TDATA
+    else:
+        data = str(transaction)
+
+    if isinstance(data, bytes):
+        header = f"{label} ({len(data)} bytes):"
+        body = _format_bytes(data, bytes_per_line=32)
+        return f"{header}\n{body}"
+    else:
+        return f"{label}:\n  {data}"
+
+
+def _compare_transactions(expected, actual, transaction_num: int = 0) -> tuple:
+    """Compare two transactions and return detailed mismatch output.
+
+    Args:
+        expected: The expected transaction from model.
+        actual: The actual transaction from DUT.
+        transaction_num: Transaction number for display.
+
+    Returns:
+        Tuple of (match: bool, message: str).
+    """
+    match = expected == actual
+
+    if match:
+        return True, ""
+
+    lines = []
+    lines.append("")
+    lines.append("=" * 70)
+    lines.append(f"Transaction #{transaction_num}: MISMATCH DETECTED")
+    lines.append("=" * 70)
+
+    msg = "\n".join(lines)
+
+    # Print expected (model) transaction
+    msg += "\n" + _format_transaction(expected, "MODEL (Expected)")
+    msg += "\n" + "-" * 70 + "\n"
+    # Print received (DUT) transaction
+    msg += _format_transaction(actual, "DUT (Received)")
+    msg += "\n" + "=" * 70
+
+    return False, msg
+
+
+class Testbench:
+    """Testbench for AXIS_PACKET_CONCATENATOR component."""
+
+    def __init__(self, dut, debug=False):
+        self.dut = dut
+        self.rx0_drv = Axi4StreamMaster(dut, "RX0_AXIS", dut.CLK)
+        self.rx1_drv = Axi4StreamMaster(dut, "RX1_AXIS", dut.CLK)
+        self.tx_mon = Axi4Stream(dut, "TX_AXIS", dut.CLK, trans_type=Axi4StreamTransaction)
+        self.backpressure = BitDriver(dut.TX_AXIS_TREADY, dut.CLK)
+
+        self.expected_output = []
+        self.scoreboard = Scoreboard(dut)
+        self.compared = 0
+
+        def compare_wrapper(actual):
+            """Compare actual output with expected, providing detailed mismatch info."""
+            if not self.expected_output:
+                cocotb.log.error("Received unexpected packet")
+                return
+            expected = self.expected_output.pop(0)
+            self.compared += 1
+            match, msg = _compare_transactions(expected, actual, self.compared)
+            if not match:
+                cocotb.log.error(msg)
+                self.scoreboard.errors += 1
+                raise AssertionError(f"Transaction mismatch detected:\n{msg}")
+            # Log success for each transaction
+            cocotb.log.debug(f"Transaction #{self.compared}: OK ({len(actual.TDATA)} bytes)")
+            return match
+
+        self.scoreboard.add_interface(self.tx_mon, self.expected_output, compare_fn=compare_wrapper)
+
+        if debug:
+            self.rx0_drv.log.setLevel(cocotb.logging.DEBUG)
+            self.rx1_drv.log.setLevel(cocotb.logging.DEBUG)
+            self.tx_mon.log.setLevel(cocotb.logging.DEBUG)
+
+    def model(self, rx0_tr: Axi4StreamTransaction, rx1_tr: Axi4StreamTransaction):
+        """Model of the DUT - concatenates two packets"""
+        concatenated = rx0_tr.TDATA + rx1_tr.TDATA
+        tx_tr = Axi4StreamTransaction()
+        tx_tr.TDATA = concatenated
+        self.expected_output.append(tx_tr)
+
+    async def reset(self):
+        self.dut.RESET.value = 1
+        await ClockCycles(self.dut.CLK, 10)
+        self.dut.RESET.value = 0
+        await RisingEdge(self.dut.CLK)

comp/axis_tools/edit/packet_concatenator/cocotb/testbench.py

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+# Makefile: Makefile to compile module
+# Copyright (C) 2024 CESNET
+# Author(s): Jakub Cabal <cabal@cesnet.cz>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+TOP_LEVEL_ENT=AXIS_PACKET_CONCATENATOR
+
+SYNTH=quartus
+export DEVICE=AGILEX
+
+.PHONY: all
+all: comp
+
+include ../../../../../build/Makefile