Merge pull request zephyrproject-rtos#20 from FrameworkComputer/pr-fwk-main-sci-delay

drivers: espi: npcx: ensure the host receives the value from eSPI VW

Author: JohnAZoidberg

drivers/espi/Kconfig.npcx

@@ -60,6 +60,19 @@ config ESPI_NPCX_PERIPHERAL_DEBUG_PORT_80_RING_BUF_SIZE
 	  The size of the ring buffer in byte used by the Port80 ISR to store
 	  Postcodes from Host.
 
+config ESPI_NPCX_VWIRE_ENABLE_SEND_CHECK
+	bool "Check the value was read by host after wire bits changed"
+	help
+	  This option enables the function to check whether the host has read the value
+	  after the wire data changes.
+
+config ESPI_NPCX_WIRE_SEND_TIMEOUT_US
+	int "eSPI virtual wire send timeout count"
+	default 1000
+	help
+	  The times to check status after sending the eSPI virtual wire signal. The unit
+	  is microseconds (µs).
+
 config ESPI_TAF_NPCX
 	bool "Nuvoton NPCX embedded controller (EC) ESPI TAF driver"
 	depends on SOC_SERIES_NPCX4
@@ -98,6 +111,14 @@ config ESPI_TAF_NPCX_RPMC_SUPPORT
 	help
 	  This option enable the handler for eSPI TAF RPMC request.
 
+config ESPI_TAF_NPCX_STS_AWAIT_TIMEOUT
+	int "A timeout value in microseconds to wait for automatic read status"
+	depends on ESPI_TAF_NPCX
+	default 20000
+	help
+	  This option specifies the timeout value in microseconds (us) for checking
+	  automatic read status.
+
 # The default value 'y' for the existing options if ESPI_NPCX is selected.
 if ESPI_NPCX
 

drivers/espi/espi_npcx.c

@@ -879,9 +879,25 @@ static int espi_npcx_send_vwire(const struct device *dev,
 	if (signal >= ESPI_VWIRE_SIGNAL_TARGET_GPIO_0) {
 		SET_FIELD(inst->VWGPSM[reg_idx], NPCX_VWEVSM_WIRE, val);
 		reg_val = inst->VWGPSM[reg_idx];
+
+		if (IS_ENABLED(CONFIG_ESPI_NPCX_VWIRE_ENABLE_SEND_CHECK)) {
+			if (!WAIT_FOR(!IS_BIT_SET(inst->VWGPSM[reg_idx], NPCX_VWEVSM_DIRTY),
+				      CONFIG_ESPI_NPCX_WIRE_SEND_TIMEOUT_US, NULL)) {
+				LOG_ERR("%s signal %d timeout", __func__, signal);
+				return -ETIMEDOUT;
+			}
+		}
 	} else {
 		SET_FIELD(inst->VWEVSM[reg_idx], NPCX_VWEVSM_WIRE, val);
 		reg_val = inst->VWEVSM[reg_idx];
+
+		if (IS_ENABLED(CONFIG_ESPI_NPCX_VWIRE_ENABLE_SEND_CHECK)) {
+			if (!WAIT_FOR(!IS_BIT_SET(inst->VWEVSM[reg_idx], NPCX_VWEVSM_DIRTY),
+				      CONFIG_ESPI_NPCX_WIRE_SEND_TIMEOUT_US, NULL)) {
+				LOG_ERR("%s signal %d timeout", __func__, signal);
+				return -ETIMEDOUT;
+			}
+		}
 	}
 
 	LOG_DBG("Send VW: %s%d 0x%08X", reg_name, reg_idx, reg_val);

drivers/espi/espi_taf_npcx.c

@@ -666,6 +666,38 @@ static void espi_taf_event_handler(const struct device *dev, struct espi_callbac
 	k_work_submit(&npcx_espi_taf_data.work);
 }
 
+int espi_taf_npcx_block(const struct device *dev, bool en_block)
+{
+	struct espi_reg *const inst = HAL_INSTANCE(dev);
+
+	if (!IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_SAF_AUTO_READ)) {
+		return 0;
+	}
+
+	if (en_block) {
+		if (WAIT_FOR(!IS_BIT_SET(inst->ESPISTS, NPCX_ESPISTS_FLAUTORDREQ),
+			     CONFIG_ESPI_TAF_NPCX_STS_AWAIT_TIMEOUT, NULL) == false) {
+			LOG_ERR("Check Automatic Read Queue Empty Timeout");
+			return -ETIMEDOUT;
+		}
+
+		inst->FLASHCTL |= BIT(NPCX_FLASHCTL_AUTO_RD_DIS_CTL);
+
+		if (WAIT_FOR(IS_BIT_SET(inst->ESPISTS, NPCX_ESPISTS_AUTO_RD_DIS_STS),
+			     CONFIG_ESPI_TAF_NPCX_STS_AWAIT_TIMEOUT, NULL) == false) {
+			inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_AUTO_RD_DIS_CTL);
+			inst->ESPISTS |= BIT(NPCX_ESPISTS_AUTO_RD_DIS_STS);
+			LOG_ERR("Check Automatic Read Disable Timeout");
+			return -ETIMEDOUT;
+		}
+	} else {
+		inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_AUTO_RD_DIS_CTL);
+		inst->ESPISTS |= BIT(NPCX_ESPISTS_AUTO_RD_DIS_STS);
+	}
+
+	return 0;
+}
+
 int npcx_init_taf(const struct device *dev, sys_slist_t *callbacks)
 {
 	espi_init_callback(&espi_taf_cb, espi_taf_event_handler, ESPI_BUS_TAF_NOTIFICATION);

soc/nuvoton/npcx/Kconfig.soc

@@ -9,4 +9,17 @@ config SOC_FAMILY_NPCX
 config SOC_FAMILY
 	default "nuvoton_npcx" if SOC_FAMILY_NPCX
 
+config NPCX_SOC_VARIANT_NPCXN
+	bool
+	select SOC_FAMILY_NPCX
+
+config NPCX_SOC_VARIANT_NPCKN
+	bool
+	select SOC_FAMILY_NPCX
+
+config NPCX_SOC_VARIANT
+	string
+	default "npcxn" if NPCX_SOC_VARIANT_NPCXN
+	default "npckn" if NPCX_SOC_VARIANT_NPCKN
+
 rsource "*/Kconfig.soc"

soc/nuvoton/npcx/common/CMakeLists.txt

@@ -1,11 +1,13 @@
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_include_directories(.)
+
 zephyr_sources_ifdef(CONFIG_PM power.c)
 zephyr_sources(
   scfg.c
-  registers.c
+  ${CONFIG_NPCX_SOC_VARIANT}/registers.c
 )
+zephyr_include_directories(${CONFIG_NPCX_SOC_VARIANT}/include)
 
 # Check for disabling header CRC.
 if (NOT DEFINED CONFIG_NPCX_HEADER_ENABLE_HEADER_CRC)

soc/nuvoton/npcx/common/npcxn/include/clock_def.h

@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2020 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _NUVOTON_NPCX_CLOCK_DEF_H_
+#define _NUVOTON_NPCX_CLOCK_DEF_H_
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <zephyr/devicetree.h>
+#include <soc_clock.h>
+
+/* FMUL clock */
+#if (OFMCLK > (MAX_OFMCLK / 2))
+#define FMCLK (OFMCLK / 2) /* FMUL clock = OFMCLK/2 */
+#else
+#define FMCLK OFMCLK /* FMUL clock = OFMCLK */
+#endif
+
+/* APBs source clock */
+#define APBSRC_CLK OFMCLK
+
+/* AHB6 clock */
+#if (CORE_CLK > (MAX_OFMCLK / 2))
+#define AHB6DIV_VAL 1 /* AHB6_CLK = CORE_CLK/2 */
+#else
+#define AHB6DIV_VAL 0 /* AHB6_CLK = CORE_CLK */
+#endif
+
+/* FIU clock divider */
+#if (CORE_CLK > (MAX_OFMCLK / 2))
+#define FIUDIV_VAL 1 /* FIU_CLK = CORE_CLK/2 */
+#else
+#define FIUDIV_VAL 0 /* FIU_CLK = CORE_CLK */
+#endif
+
+#if defined(CONFIG_CLOCK_CONTROL_NPCX_SUPP_FIU1)
+#if (CORE_CLK > (MAX_OFMCLK / 2))
+#define FIU1DIV_VAL 1 /* FIU1_CLK = CORE_CLK/2 */
+#else
+#define FIU1DIV_VAL 0 /* FIU1_CLK = CORE_CLK */
+#endif
+#endif /* CONFIG_CLOCK_CONTROL_NPCX_SUPP_FIU1 */
+
+/* I3C clock divider */
+#if (OFMCLK == MHZ(120)) /* MCLkD must between 40 mhz to 50 mhz*/
+#define MCLKD_SL 2       /* I3C_CLK = (MCLK / 3) */
+#elif (OFMCLK <= MHZ(100) && OFMCLK >= MHZ(80))
+#define MCLKD_SL 1 /* I3C_CLK = (MCLK / 2) */
+#else
+#define MCLKD_SL 0 /* I3C_CLK = MCLK */
+#endif
+
+/* Get APB clock freq */
+#define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1))
+
+/*
+ * Frequency multiplier M/N value definitions according to the requested
+ * OFMCLK (Unit:Hz).
+ */
+#if (OFMCLK > (MAX_OFMCLK / 2))
+#define HFCGN_VAL 0x82 /* Set XF_RANGE as 1 */
+#else
+#define HFCGN_VAL 0x02
+#endif
+#if (OFMCLK == 120000000)
+#define HFCGMH_VAL 0x0E
+#define HFCGML_VAL 0x4E
+#elif (OFMCLK == 100000000)
+#define HFCGMH_VAL 0x0B
+#define HFCGML_VAL 0xEC
+#elif (OFMCLK == 96000000)
+#define HFCGMH_VAL 0x0B
+#define HFCGML_VAL 0x72
+#elif (OFMCLK == 90000000)
+#define HFCGMH_VAL 0x0A
+#define HFCGML_VAL 0xBA
+#elif (OFMCLK == 80000000)
+#define HFCGMH_VAL 0x09
+#define HFCGML_VAL 0x89
+#elif (OFMCLK == 66000000)
+#define HFCGMH_VAL 0x07
+#define HFCGML_VAL 0xDE
+#elif (OFMCLK == 50000000)
+#define HFCGMH_VAL 0x0B
+#define HFCGML_VAL 0xEC
+#elif (OFMCLK == 48000000)
+#define HFCGMH_VAL 0x0B
+#define HFCGML_VAL 0x72
+#else
+#error "Unsupported OFMCLK Frequency"
+#endif
+
+/* Clock prescaler configurations in different series */
+#define VAL_HFCGP ((FPRED_VAL << 4) | AHB6DIV_VAL)
+#if defined(FIU1DIV_VAL)
+#define VAL_HFCBCD ((FIU1DIV_VAL << 4) | (FIUDIV_VAL << 2))
+#else
+#define VAL_HFCBCD (FIUDIV_VAL << 4)
+#endif /* FIU1DIV_VAL */
+#define VAL_HFCBCD1 (APB1DIV_VAL | (APB2DIV_VAL << 4))
+#if defined(APB4DIV_VAL)
+#define VAL_HFCBCD2 (APB3DIV_VAL | (APB4DIV_VAL << 4))
+#else
+#define VAL_HFCBCD2 APB3DIV_VAL
+#endif /* APB4DIV_VAL */
+/* I3C1~I3C3 share the same configuration */
+#define VAL_HFCBCD3 MCLKD_SL
+
+#endif /* _NUVOTON_NPCX_CLOCK_DEF_H_ */