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Description
Describe the bug
Verilator linter does not show any issues or warnings n Verilog or SystemVerilog files.
To Reproduce
- Install verilator under MSYS2/Mingw64 on Windows
- Enable Linter Settings > Verilog/SV Linter: Verilator in TerosHDL Global Config
- Open any verilog .v file in VSCode
- Check Output > TerosHDL: Debug, it shows:
2025-09-27 18:35:31.309 [info] Linting with command: verilator --lint-only -Wall -bbox-sys --bbox-unsup -DGLBL -Irtl/verilog/lib -Iverif/lib "c:\dev\hdl\rtl\verilog\fp16\fp16_add.v"
2025-09-27 18:35:31.422 [info] c:\dev\hdl\rtl\verilog\fp16\fp16_add.v || 'verilator' is not recognized as an internal or external command, operable program or batch file.
Code
Any verilog file
Please complete the following information:
- OS: Windows 11
- VSCode version version 1.104.2
Additional context
Copy-pasting the listed command to git bash terminal runs fine.
verilator --lint-only -Wall -bbox-sys --bbox-unsup -DGLBL -Irtl/verilog/lib -Iverif/lib "c:\dev\hdl\rtl\verilog\fp16\fp16_add.v"
%Warning-WIDTHTRUNC: c:\dev\hdl\rtl\verilog\fp16\fp16_add.v:191:27: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits.
: ... note: In instance 'fp16_add'
191 | shift_val = 24 - msb_pos;
| ^
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.040
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.It works ok and lists issues and warnings it can find in Verilog code.
However, Windows CMD does not run that same command, probably because verilator is a Perl wrapper over verilator_bin.exe and Windows has no idea how to execute it. I suspect it is the core of the problem for TerosHDL.
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