Lower case for auto completion?

[musmuris]

Hi,
When I start typing (e.g.) std_logic_vector VSCode is offering me auto-completions, but they are all in UPPERCASE - so STD_LOGIC_VECTOR etc. The code style we use is all lower case (and a quick check on t'internet shows this is common?) - is there anyway to get Teros to offer lower case options?

(turning off Teros dropped all the options so I think it's coming from there rather than other extension)

[atticlabsdesign]

Spent all day today struggling with this myself, teroshdl always runs vhdl-ls (a.k.a. vhdl_ls, a.k.a rust_hdl) in the background with vhdl files, even if the formatter is set to vsg and the linter is set to disabled. by default vhdl-ls uses all caps for type completion, the latest version0.86.0 has support for lower case formatting, by adding preferred_case = "lower" to the vhdl_ls.toml it uses for configuration.

i successfully updated the builtin version of the language server to 0.86.0 but it does not abide by the vhdl-ls documentation which states that the .toml fille can go in the root directory of the project. since the toml can contain information about vhdl libraries terosHDL actually makes its own temorary file which generates the libraries based on the teroshdl project. I have been unable to hack the extension so far to get this functionality to work but it should. I set up VHDL by HGB to correctly use lower case with the latest ls but unfortunately since there is no way to disable the language server in teroshdl without deactivating the whole extension vscode was pretty unhappy lol

I have made a feature request #847 (comment).

unfortunately i am not familiar with extensions enough to make my own fix and PR.

To be honest with you i wish this wasnt a monolithic extension for this reason, I like it for combining the simulation and visualization, but it comes with too much builtin it feels like, id rather it be a pack of multiple extensions.

[atticlabsdesign]

update lol my fork now has this functionality, it was too annoying to not fix https://github.com/Attic-Labs-Design/vscode-terosHDL. the setting is now based on your keyword case setting under Formatter -> VHDL standalone -> Keyword case

[atticlabsdesign]

realized i misinterpreted the case settings, i changed it to use the name case setting