Does cache IP support for TAPA async-Mem interfaces?

[AndyNie-zz]

In Vitis HLS, a cache can be configured for memory interfaces. Does the TAPA async-mem interface also provide a cache IP? Alternatively, is it possible to use the cache IP officially provided by Vitis for async-mem?

[UbaidHunts]

It looks like Tapa async-mem interface only provides interface for HBM or DDR memory