ghostwrite_openc910_simulation

openC910 Analysis

Unfortunately, this part of the artifact depends on running a x86 binary, as T-Head only provides smart_run/tests/bin/Srec2vmem statically compiled for x86. On other architectures you can fall back to binfmt.

Caution

As this part of the artifact executes non-auditable code, we recommend running it in a container.

Nix again provides the environment for this experiment. Run direnv allow to load the environment. The environment uses the vendor-provided XuanTie toolchain packaged in Xuantie-900-gcc-elf-newlib-x86_64-V2.0.3-20210806.tar.gz. Nix automatically makes that toolchain usable on (hopefully) every system.

Core compilation

First, the core has to be compiled. This time we use verilator for faster running of the test cases at the expense of compilation time:

make -C smart_run compile SIM=verilator

This takes 5-20 minutes.

Expected output:

[THead-smart] Compiling smart now ...
[THead-smart] SIM = verilator
...
[THead-smart] Compilation finished!

This should produce a file smart_run/work/obj_dir/Vtop, the compiled core.

Running the Vector Test

Running the vector test can be done like:

make -C smart_run runcase SIM=verilator CASE=c910_test_vector

Expected output:

	********* Init Program *********
	********* Wipe memory to 0 *********
	********* Read program *********
	********* Load program to memory *********
Enabling FPU and vector unit...
Division works: 0.300000
Finished successfully!
**********************************************
*    simulation finished successfully        *
**********************************************

The simulation should terminate cleanly.

Now run the same program, but this time run a vector instruction:

make -C smart_run runcase SIM=verilator CASE=c910_test_vector RUN_VECTOR_INSTR=1

Expected output:

	********* Init Program *********
	********* Wipe memory to 0 *********
	********* Read program *********
	********* Load program to memory *********
Enabling FPU and vector unit...
Division works: 0.300000
**********************************************
*    simulation finished with error          *
**********************************************

This time the simulation fails, indicating that the vector extension cannot be properly enabled in the provided core.

Original Readme Following

IP Readme

Welcome to C910! Some key directories are shown below.

|--C910_RTL_FACTORY/
  |--gen_rtl/     ## Verilog source code of C910
  |--setup/       ## Script to set the environment variables
|--smart_run/     ## RTL simulation environment
  |--impl/        ## SDC file, scripts and file lists for implementation
  |--logical/     ## SoC demo and test bench to run the simulation
  |--setup/       ## GNU tool chain setting
  |--tests/       ## Test driver and test cases
  |--work/        ## Working directory for builds
  |--Makefile     ## Makefile for building and running sim targets
|--doc/           ## The user and integration manual of C910

Usage

Step1: Get Started

$ cd C910_RTL_FACTORY
$ source setup/setup.csh
$ cd ../smart_run
$ make help
To gain more information about how to use smart testbench.

Step2: Download and install C/C++ Compiler

You can download the GNU tool chain compiled by T-HEAD from the url below:
https://occ.t-head.cn/community/download?id=3948120165480468480

$ cd ./smart_run
GNU tool chain (specific riscv version) must be installed and specified before
compiling *.c/*.v tests of the smart environment. Please refer to the following
setup file about how to specify it:
    ./smart_run/setup/example_setup.csh

Notes

The testbench supports Verilator(version is better newer than 4.215),iverilog, vcs and irun to run simulation and you can use Gtkwave or verdi
to open the waveform under ./smart_run/work/ directory.

You can get the debugger, IDE and SDK from the url:https://occ.t-head.cn/community/download?id=575997419775328256

Discussion

If you are interested in participating in discussions or improving the "openXuantie" cores, you can scan the DingDing QR code below to join the discussion group.

/*Copyright 2019-2021 T-Head Semiconductor Co., Ltd.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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