[Feature Request] Add Huawei Ascend NPU Hardware Acceleration Support

[autoxj]

Hello FAISS community,

We have implemented an experimental backend for FAISS that enables vector search algorithms to run on Huawei Ascend NPUs. This is achieved through the Ascend Computing Language (ACL) interface, leveraging the AICORE's compute power for operations like distance calculations and index traversal (e.g., Flat).

Given FAISS's role as a foundational library for efficient similarity search, we believe adding NPU support could provide the community with a valuable new hardware acceleration option. Our implementation aims to follow FAISS's design patterns (e.g., similar to the GPU resource abstraction) to ensure clean integration.

We hope to contribute this work upstream. Before proceeding, we seek the maintainers' guidance on:

Whether there is interest in adding an NPU backend.

The preferred integration approach and any architectural constraints.

The required testing and benchmarking standards.

[mdouze]

Hello @autoxj

Thanks for your interest in Faiss and the offer to port it to the Ascend platform.
Are you a Huawei employee? What would you like to achieve by adding the support for the platform to Faiss?

On our side, we try to support major hardware platforms, even if we don't necessarily deploy them at Meta.

This entails:

• adding code, which can be quite involved if it is a co-processor rather than a CPU instruction set extension.
• get a reasonable coverage of the Faiss indexes (ie. just IndexFlat is not worthwhile)
• the submitter will support the code for the foreseeable future: responding to our requests and to issues related to the code
• implement tests and provide a cloud machine that can be reached by github actions so that the tests can be run automatically when the code changes.

This is why support for new platforms is usually provided by the hardware developers themselves.

[autoxj]

Hello @mdouze

Thank you very much for your detailed and thoughtful response! I truly appreciate the guidance you've provided regarding the Ascend NPU support for Faiss.

To ensure I provide you with comprehensive and accurate information, I need to coordinate with my team to confirm several implementation details, resource commitments, and testing plans. This will help us present a solid proposal that addresses all your requirements.

I'll follow up with a detailed response within the next 2-3 weeks, covering our implementation roadmap, index coverage plans, long-term support strategy, and CI integration approach.

In the meantime, if you have any additional questions or specific aspects you'd like me to focus on in my detailed response, please feel free to let me know.

Looking forward to continuing this conversation and collaborating with you on expanding Faiss's hardware ecosystem.

Best regards

[autoxj]

Hello, we are actively advancing NPU-related development work. We have completed the basic resource management framework (following the GPU implementation pattern, achieving similar resource abstraction through the ACL interface). However, we are currently addressing a critical issue: optimizing the NPU operator compilation and packaging workflow . This directly impacts the library’s usability—including simplifying environment configuration, standardizing the compilation process, and ensuring the integrity of the packaged library.

We believe that only by resolving these engineering challenges can NPU support truly become a community-usable feature. Once we complete this work, we will immediately follow up with you to share more detailed implementation specifics, test results, and integration plans, collaborating to advance the upstream contribution of this feature.