Analysis tool on VHDL/VERILOG extenal component (error!)

[dat-alex]

I am trying to run Analysis tool (F9) on a design tha includes externl VERILOG component with no success!
I guess Analyusis is not supported on external HDL/Verilog components?

Thank you for your time,
Alexandros (GREECE)

[hneemann]

That's true. Analysis of VHDL/Verilog components is not supported.