Merge branch 'verilog-importer-fixes'

hagantsa · hagantsa · commit d845eea1e874 · 2026-06-25T09:48:54.000+03:00
diff --git a/Plugins/VerilogImport/VerilogParameterParser.cpp b/Plugins/VerilogImport/VerilogParameterParser.cpp
@@ -31,7 +31,7 @@
 
 namespace
 {
-    const QRegularExpression TYPE_RULE("(\\w+)\\s+(?:(" + VerilogSyntax::RANGE + ")?\\s*(" + 
+    const QRegularExpression TYPE_RULE("(?:localparam|parameter)?\\s*((?:\\w|:)+\\s+)?((?:\\w|:)+)?\\s*(?:(" + VerilogSyntax::RANGE + ")?\\s*(" + 
         VerilogSyntax::RANGE + "))?\\s*" + VerilogSyntax::NAME_VALUE, QRegularExpression::CaseInsensitiveOption);
 }
 
@@ -63,12 +63,19 @@ void VerilogParameterParser::setHighlighter(Highlighter* highlighter)
 void VerilogParameterParser::import(QString const& componentDeclaration, QSharedPointer<Component> targetComponent,
     QSharedPointer<ComponentInstantiation> targetComponentInstantiation)
 {
-    QStringList declarations = findDeclarations(componentDeclaration);
+    auto declarations = findDeclarations(componentDeclaration);
 
-    QList<QSharedPointer<ModuleParameter> > parsedParameters;
-    for (QString const& declaration : declarations)
+    QList<QPair<QSharedPointer<ModuleParameter>, QString> > parsedParameters; // For mapping parameter type (localparam/parameter) to parsed parameter
+    for (auto const& declaration : declarations)
     {
-        parsedParameters.append(parseParameters(declaration));
+        auto params = parseParameters(declaration.value_);
+
+        // In most cases size of params should be 1
+        std::for_each(params.begin(), params.end(),
+            [&declaration, &parsedParameters](QSharedPointer<ModuleParameter> moduleParam)
+            {
+                parsedParameters.append(std::make_pair(moduleParam, declaration.type_));
+            });
     }
 
     if (targetComponentInstantiation.isNull() == false)
@@ -90,7 +97,11 @@ void VerilogParameterParser::import(QString const& componentDeclaration, QShared
             }
         }
 
-        targetComponentInstantiation->getModuleParameters()->append(parsedParameters);
+        std::for_each(parsedParameters.cbegin(), parsedParameters.cend(),
+            [&targetComponentInstantiation](auto const& pair)
+            {
+                targetComponentInstantiation->getModuleParameters()->append(pair.first);
+            });
     }
 
     replaceNamesReferencesWithIds(parsedParameters, targetComponent, targetComponentInstantiation);
@@ -99,7 +110,8 @@ void VerilogParameterParser::import(QString const& componentDeclaration, QShared
 //-----------------------------------------------------------------------------
 // Function: VerilogParameterParser::findDeclarations()
 //-----------------------------------------------------------------------------
-QStringList VerilogParameterParser::findDeclarations(QString const& input)
+// QStringList VerilogParameterParser::findDeclarations(QString const& input)
+QList<VerilogParameterParser::ParameterDeclaration> VerilogParameterParser::findDeclarations(QString const& input)
 {    
     return findParameterDeclarations(input, findParameterSection(input));
 }
@@ -146,6 +158,15 @@ QList<QSharedPointer<ModuleParameter> > VerilogParameterParser::parseParameters(
 
     // Find the type and the declaration. Only one per declaration is supported.
     QString type = parseType(input);
+    QString typeWithModifier = type;
+    QString signingModifier = TYPE_RULE.match(input).captured(2);
+
+    // Create complete type if there is a sign modifier
+    if (QRegularExpression("(signed|unsigned)").match(signingModifier.toLower()).hasMatch())
+    {
+        typeWithModifier.append(QStringLiteral(" ") % signingModifier); // e.g. int unsigned
+    }
+
     QString bitWidthLeft = parseBitWidthLeft(input);
     QString bitWidthRight = parseBitWidthRight(input);
     QString arrayLeft = parseArrayLeft(input);
@@ -156,7 +177,7 @@ QList<QSharedPointer<ModuleParameter> > VerilogParameterParser::parseParameters(
     inputWithoutComments.remove(QRegularExpression(VerilogSyntax::COMMENT));
 
     QString parameterDefinition =  "(" + VerilogSyntax::NAMES + ")\\s*=((\\s*(" + 
-        VerilogSyntax::OPERATION_OR_ALPHANUMERIC + ")+\\s*)+)";
+        VerilogSyntax::PARAMETER_VALUE + ")+\\s*)+)";
 
     QRegularExpression parameterRule(parameterDefinition + "(\\s*,\\s*" + parameterDefinition + ")*", 
         QRegularExpression::CaseInsensitiveOption);    
@@ -177,7 +198,7 @@ QList<QSharedPointer<ModuleParameter> > VerilogParameterParser::parseParameters(
         // Each name value pair produces a new module parameter, but the type and the description is recycled.
         QSharedPointer<ModuleParameter> moduleParameter =  QSharedPointer<ModuleParameter>(new ModuleParameter());      
         moduleParameter->setName(name);
-        moduleParameter->setDataType(type);
+        moduleParameter->setDataType(typeWithModifier);
         moduleParameter->setType(createTypeFromDataType(type));
         moduleParameter->setValue(value);
         moduleParameter->setUsageType("nontyped");
@@ -211,39 +232,41 @@ QString VerilogParameterParser::createTypeFromDataType(QString const& dataType)
 //-----------------------------------------------------------------------------
 // Function: VerilogParameterParser::findDeclarations()
 //-----------------------------------------------------------------------------
-QStringList VerilogParameterParser::findParameterDeclarations(QString const& componentDeclaration,
+// QStringList VerilogParameterParser::findParameterDeclarations(QString const& componentDeclaration,
+QList<VerilogParameterParser::ParameterDeclaration > VerilogParameterParser::findParameterDeclarations(QString const& componentDeclaration,
     QString const& parameterArea)
 {
     // List of detected parameter declarations.
-    QStringList declarations;
+    QList<ParameterDeclaration> declarations;
 
     // Rule used to detect parameter declarations.
-    QRegularExpression declarationRule("\\bparameter\\s+.*(?:"
+    QRegularExpression declarationRule("\\b(localparam|parameter)\\s+.*(?:"
         "(;[ \\t]*" + VerilogSyntax::COMMENT + ")|"
         "(;|$)|"
-        "(,([ \\t]*" + VerilogSyntax::COMMENT +")?(?=\\s*\\bparameter\\b)))",
+        "(,([ \\t]*" + VerilogSyntax::COMMENT +")?(?=\\s*\\b(?:localparam|parameter)\\b)))",
         QRegularExpression::CaseInsensitiveOption | QRegularExpression::InvertedGreedinessOption |
         QRegularExpression::DotMatchesEverythingOption);
-
+    
     QRegularExpression commentBegin(QStringLiteral("//"));
     QRegularExpression lineBegin(QStringLiteral("^|\\r?\\n"));
 
     QRegularExpressionMatchIterator iter = declarationRule.globalMatch(parameterArea);
     while (iter.hasNext())
     {        
         QRegularExpressionMatch match = iter.next();
-        QString declaration = match.captured();
+        auto fullDeclaration = match.captured();
+        auto paramType = match.captured(1); // get the param type: localparam or parameter
         int declarationBegin = match.capturedStart();
 
         // Check keyword parameter is not inside a comment.
         if (parameterArea.lastIndexOf(lineBegin, declarationBegin) > parameterArea.lastIndexOf(commentBegin, declarationBegin))
         {
             if (highlighter_)
             {
-                highlighter_->applyHighlight(declaration, KactusColors::Importer::MODELPARAMETER, componentDeclaration);
+                highlighter_->applyHighlight(fullDeclaration, KactusColors::Importer::MODELPARAMETER, componentDeclaration);
             }
 
-            declarations.append(declaration);
+            declarations.append(ParameterDeclaration{paramType, fullDeclaration});
         }
     }
 
@@ -270,7 +293,7 @@ QString VerilogParameterParser::parseType(QString const& input)
 //-----------------------------------------------------------------------------
 QString VerilogParameterParser::parseBitWidthLeft(QString const& declaration)
 {
-    QString bitRange = TYPE_RULE.match(declaration).captured(3);
+    QString bitRange = TYPE_RULE.match(declaration).captured(4);
 
     QRegularExpressionMatch rangeMatch = VerilogSyntax::CAPTURING_RANGE.match(bitRange);
     QString left = rangeMatch.captured(1);
@@ -283,7 +306,7 @@ QString VerilogParameterParser::parseBitWidthLeft(QString const& declaration)
 //-----------------------------------------------------------------------------
 QString VerilogParameterParser::parseBitWidthRight(QString const& declaration)
 {
-    QString bitRange = TYPE_RULE.match(declaration).captured(3);
+    QString bitRange = TYPE_RULE.match(declaration).captured(4);
 
     QRegularExpressionMatch rangeMatch = VerilogSyntax::CAPTURING_RANGE.match(bitRange);
     QString right = rangeMatch.captured(2);
@@ -296,7 +319,7 @@ QString VerilogParameterParser::parseBitWidthRight(QString const& declaration)
 //-----------------------------------------------------------------------------
 QString VerilogParameterParser::parseArrayLeft(QString const& declaration)
 {
-    QString bitRange = TYPE_RULE.match(declaration).captured(2);
+    QString bitRange = TYPE_RULE.match(declaration).captured(3);
 
     return VerilogSyntax::CAPTURING_RANGE.match(bitRange).captured(1);
 }
@@ -306,7 +329,7 @@ QString VerilogParameterParser::parseArrayLeft(QString const& declaration)
 //-----------------------------------------------------------------------------
 QString VerilogParameterParser::parseArrayRight(QString const& declaration)
 {
-    QString bitRange = TYPE_RULE.match(declaration).captured(2);
+    QString bitRange = TYPE_RULE.match(declaration).captured(3);
 
     return VerilogSyntax::CAPTURING_RANGE.match(bitRange).captured(2);
 }
@@ -345,10 +368,10 @@ QString VerilogParameterParser::parseDescription(QString const& input)
 //-----------------------------------------------------------------------------
 // Function: VerilogParameterParser::copyIdsFromOldModelParameters()
 //-----------------------------------------------------------------------------
-void VerilogParameterParser::copyIdsFromOldModelParameters(QList<QSharedPointer<ModuleParameter> > parsedParameters,
+void VerilogParameterParser::copyIdsFromOldModelParameters(QList<QPair<QSharedPointer<ModuleParameter>, QString> > parsedParameters,
     QSharedPointer<ComponentInstantiation> targetComponentInstantiation)
 {
-    for (QSharedPointer<ModuleParameter> parameter : parsedParameters)
+    for (auto const& [parameter, type] : parsedParameters)
     {
 		for (QSharedPointer<ModuleParameter> existingParameter :
             *targetComponentInstantiation->getModuleParameters())
@@ -366,14 +389,14 @@ void VerilogParameterParser::copyIdsFromOldModelParameters(QList<QSharedPointer<
 // Function: VerilogParameterParser::replaceReferenceNamesWithIds()
 //-----------------------------------------------------------------------------
 void VerilogParameterParser::replaceNamesReferencesWithIds(
-    QList<QSharedPointer<ModuleParameter> > parsedParameters,
+    QList<QPair<QSharedPointer<ModuleParameter>, QString> > const& parsedParameters,
     QSharedPointer<Component> targetComponent,
 	QSharedPointer<ComponentInstantiation> targetComponentInstantiation)
 {
-    for (QSharedPointer<ModuleParameter> moduleParameter : parsedParameters)
+    for (auto const& [moduleParameter, type] : parsedParameters)
     {
         QSharedPointer<Parameter> targetParameter = 
-            Search::findByName(moduleParameter->name(), *targetComponent->getParameters()); 
+            Search::findByName(moduleParameter->name(), *targetComponent->getParameters());
 
         if (targetParameter.isNull())
         {
@@ -391,6 +414,12 @@ void VerilogParameterParser::replaceNamesReferencesWithIds(
         targetParameter->setDescription(moduleParameter->description());
         targetParameter->increaseUsageCount();
 
+        if (type.compare(QStringLiteral("localparam")) == 0)
+        {
+            targetParameter->setValueResolve(QStringLiteral("immediate"));
+            moduleParameter->setValueResolve(QStringLiteral("immediate"));
+        }
+
         moduleParameter->setValue(targetParameter->getValueId());
     }
     
@@ -416,7 +445,7 @@ void VerilogParameterParser::replaceNameReferencesWithParameterIds(QSharedPointe
 {
     foreach (QSharedPointer<Parameter> define, *targetComponent->getParameters())
     {
-        QRegularExpression macroUsage("`?" + define->name() + "\\b");
+        QRegularExpression macroUsage("`?" + define->name() + "(?![\\._])"); // don't match systemverilog struct field accesses, e.g MyStruct.field, and other things that can cause partial match
 
         QString parameterValue = replaceNameWithId(parameter->getValue(), macroUsage, define);
         parameter->setValue(parameterValue);
diff --git a/Plugins/VerilogImport/VerilogParameterParser.h b/Plugins/VerilogImport/VerilogParameterParser.h
@@ -31,6 +31,13 @@ class VerilogParameterParser : public HighlightSource
 {
 public:
 
+    //! Describes a single (system)verilog module parameter declaration found in module
+    struct ParameterDeclaration
+    {
+        QString type_; // parameter or localparam
+        QString value_;
+    };
+
     //! The constructor.
     VerilogParameterParser();
 
@@ -65,7 +72,7 @@ class VerilogParameterParser : public HighlightSource
      *
      *    @return   The resulting list of parameter declarations.
      */
-    QStringList findDeclarations(QString const& input);
+    QList<ParameterDeclaration> findDeclarations(QString const& input);
 
     /*!
      *  Parses parameters out of declaration.
@@ -95,7 +102,8 @@ class VerilogParameterParser : public HighlightSource
      *
      *    @return   The resulting list of declarations.
      */
-     QStringList findParameterDeclarations(QString const& componentDeclaration, QString const& parameterArea);
+    //  QStringList findParameterDeclarations(QString const& componentDeclaration, QString const& parameterArea);
+     QList<ParameterDeclaration> findParameterDeclarations(QString const& componentDeclaration, QString const& parameterArea);
 
     /*!
      *  Create an IP-XACT type for the parameter according to the given data type.
@@ -166,15 +174,15 @@ class VerilogParameterParser : public HighlightSource
       *    @param [in] parsedParameters   The parsed model parameters.
       *    @param [in] targetComponent    The component to import to.
       */
-     void copyIdsFromOldModelParameters(QList<QSharedPointer<ModuleParameter> > parsedParameters,
+     void copyIdsFromOldModelParameters(QList<QPair<QSharedPointer<ModuleParameter>, QString> > parsedParameters,
          QSharedPointer<ComponentInstantiation> targetComponentInstantiation);
 
      /*!
       *  Replaces the referenced model parameter names with their ids in model parameter values.
       *
       *    @param [in] targetComponent   The component whose model parameter values to replace.
       */
-     void replaceNamesReferencesWithIds(QList<QSharedPointer<ModuleParameter> > parsedParameters,
+     void replaceNamesReferencesWithIds(QList<QPair<QSharedPointer<ModuleParameter>, QString> > const& parsedParameters,
          QSharedPointer<Component> targetComponent,
          QSharedPointer<ComponentInstantiation> targetComponentInstantiation);
 
diff --git a/Plugins/VerilogImport/VerilogPortParser.cpp b/Plugins/VerilogImport/VerilogPortParser.cpp
@@ -63,7 +63,7 @@ namespace
         "(" + VerilogSyntax::NAMES + ")\\s*[;](?:[ \\t]*"+ VerilogSyntax::COMMENT + ")?");
 
 	//! Declaration for verilog parameters.
-	const QString MODULE_PARAMETER_DECLARATION("\\s*#\\((\\s*parameter.*)+\\s*\\)");
+    const QString MODULE_PARAMETER_DECLARATION("\\s*#\\(([\\s\\S]*?)\\)"); // just match the parameter list section, not the stuff inside (allow e.g. system verilog localparams)
 
     //! Port declaration for Verilog-1995 style.
     const QString PORT_DECLARATION_1995("\\((\\s*\\w*,)*\\s*\\w+\\s*\\);");
@@ -75,13 +75,13 @@ namespace
     const QString DECLARATION_1995(MODULE_AND_PARAMETERS_DECLARATION + PORT_DECLARATION_1995);
 
     //! Modified module declaration for use in checking ports
-    const QString NEW_MODULE_DECLARATION("(?:^|\\r?\\n)[ \t]*(?:macro)?module\\s*\\w*");
+    const QString NEW_MODULE_DECLARATION("(?:^|\\r?\\n)[ \t]*(?:macro)?module\\s+\\w+");
 
     //! Everything after module and parameter declaration.
     const QString MODULE_DECLARATION_REST("\\s*\\([^;]*");
 
     //! Full declaration of a verilog module.
-    const QString FULL_MODULE_DECLARATION(NEW_MODULE_DECLARATION + "(" + MODULE_PARAMETER_DECLARATION + ")?" + MODULE_DECLARATION_REST);
+    const QString FULL_MODULE_DECLARATION(NEW_MODULE_DECLARATION + "(" + MODULE_PARAMETER_DECLARATION  + ")?" + MODULE_DECLARATION_REST);
 }
 
 //-----------------------------------------------------------------------------
diff --git a/Plugins/VerilogImport/VerilogSyntax.h b/Plugins/VerilogImport/VerilogSyntax.h
@@ -57,7 +57,10 @@ namespace VerilogSyntax
 
     //! An expression that may contain an operator or an alphanumeric symbol.
     const QString OPERATION_OR_ALPHANUMERIC("({[^}]*})|([$<>+*\\(\\)\\{\\}/-])|([']?[{(])|(`?\\w+)|((\\w+)?'\\w+)|\"\\w+\"");
-    
+
+    //! Expression for parameter value, accepts systemverilog style types with class scope (operator ::) and struct accessor (operator ., e.g. mystruct.var)
+    const QString PARAMETER_VALUE("({[^}]*})|([$<>+*\\(\\)\\{\\}/-])|([']?[{(])|((\\w+)?'\\w+)|\"\\w+\"|(`?(?:\\d+|[A-Za-z_]\\w*(?:(?:::|.)[A-Za-z_]\\w*)*))");
+
     //! Name + value pair, e.g. name=value.
     const QString NAME_VALUE = "\\w+\\s*=(\\s*(" + OPERATION_OR_ALPHANUMERIC + "))+";  
 
diff --git a/tests/Plugins/VerilogImport/tst_VerilogParameterParser.cpp b/tests/Plugins/VerilogImport/tst_VerilogParameterParser.cpp
