[ROCm] Add AMD GPU support via HIP

[jeffdaily]

This adds an AMD GPU build path to cupoch using HIP/ROCm, behind a new option(USE_HIP OFF). It builds the same module set as the CUDA build: the GPU compute modules, the OpenGL visualization, and the pybind11 Python module. The default NVIDIA CUDA build is unchanged -- every addition is guarded by USE_HIP / #if defined(USE_HIP), so a build without the flag compiles the same sources through nvcc as before.

Suggested review order:

1. CMakeLists.txt and cmake/. cupoch drives every GPU library through the legacy FindCUDA module (cuda_add_library, CUDA_NVCC_FLAGS). Under USE_HIP we enable_language(HIP) and define a cuda_add_library() shim that creates a normal library and marks its sources LANGUAGE HIP, so the per-module CMakeLists files are untouched. The GPU architecture is detected by CMake and only defaulted when unset (never hardcoded). Because the upstream third_party/CMakeLists.txt bakes in FindCUDA assumptions, the USE_HIP build assembles its dependency graph through cmake/cupoch_hip_3rdparty.cmake and its module set through cmake/cupoch_hip_modules.cmake; the small compat shims under cmake/ adapt the vendored stdgpu/flann/lbvh trees to ROCm 7 without editing those submodules. USE_RMM (RAPIDS, CUDA-only) is forced OFF under USE_HIP via cmake_dependent_option and falls back to thrust::device_vector.

2. src/cupoch/utility/cuda_to_hip.h. The single point of CUDA<->HIP runtime translation: it aliases the cuda* runtime symbols cupoch uses (including the GL-interop entry points, which ROCm provides as hipGraphics*) to their hip* spellings and includes the HIP runtime; on NVIDIA it is a plain #include <cuda_runtime.h>. The remaining source edits route their CUDA runtime / Thrust includes through it and fix rocThrust spelling differences (thrust::hip::par, the pinned allocator, value-init of HIP vector types) and a few clang/HIP strictness issues (host/device attribute matching on the geometry .inl headers, a shared aggregate in the distance transform).

Two features are not available on the ROCm build and are skipped automatically (no user flag), with the rest of the library unaffected:

• the libSGM-based stereo matcher in imageproc (libSGM is CUDA-only); and
• ScalableTSDFVolume, whose device hash map stores a volume unit that exceeds the AMD GPU per-work-item scratch limit. UniformTSDFVolume is unaffected.

Test Plan:

Built from a clean tree and validated on real AMD GPUs -- gfx90a (CDNA2) and gfx1100 (RDNA3) on Linux, and gfx1201 (RDNA4) on Windows -- with ROCm 7.2.1:

cmake <src> -DUSE_HIP=ON -DCMAKE_BUILD_TYPE=Release
cmake --build . -j

All module libraries plus the Python extension build with no errors. GPU correctness was exercised through the Python module on a fixed point cloud (AMD_LOG_LEVEL=3 confirmed real device dispatches, not a CPU fallback), with a CPU reference or known-answer check per module:

• geometry: VoxelDownSample centroids match a CPU grid-bin reference to float epsilon and are bitwise-identical across runs; EstimateNormals match a CPU KNN+covariance reference (worst |dot| = 0.999998).
• registration: point-to-plane ICP recovers an injected transform (fitness 1.0, rmse 0), deterministic; GeneralizedICP runs.
• integration (UniformTSDFVolume), collision, io (PLY roundtrip, 0 error), odometry, and planning each run on GPU with sane/deterministic results.

The default CUDA path (USE_HIP=OFF) was compile-checked with nvcc 12.8 (sm_80); it has not been run on NVIDIA hardware. Every source the port touches compiles cleanly under nvcc in its USE_HIP=OFF form, confirming the guards are scoped so the CUDA build sees the original code.

This work was authored with assistance from Claude (Anthropic).

[neka-nat]

Great job!!