STVAL_WIDTH has no minimum and a nonsensical 2^64-1 maximum for a bit-width (should mirror MTVAL_WIDTH: 0..64)

[uditjainstjis]

Describe the bug

spec/std/isa/param/STVAL_WIDTH.yaml bounds the parameter as:

schema:
  type: integer
  maximum: 18446744073709551615 # 2^64 - 1

with no minimum. STVAL_WIDTH is "the number of implemented bits in stval", so its value is a bit width, not a byte count. The privileged spec states the register is at most SXLEN bits wide:

"The stval CSR is an SXLEN-bit read-write register ..." — riscv-isa-manual src/priv/supervisor.adoc (norm anchor near line 709)

Since SXLEN is 32 or 64, a stval width of 2^64 - 1 bits is not representable and the upper bound is meaningless. The 2^64 - 1 idiom is appropriate for a byte-size parameter (e.g. CACHE_BLOCK_SIZE) but was misapplied to a bit-width here.

Expected

The bound should match the M-mode twin MTVAL_WIDTH.yaml, which models the identical concept (implemented bits in mtval) correctly:

schema:
  type: integer
  minimum: 0
  maximum: 64

STVAL_WIDTH should be brought to parity: minimum: 0, maximum: 64. Its long_name is also the placeholder TODO, where MTVAL_WIDTH has Width of the mtval CSR.

Proposed fix

Bring STVAL_WIDTH to parity with MTVAL_WIDTH:

• schema.minimum: 0, schema.maximum: 64
• long_name: "Width of the stval CSR"

Follow-up (needs maintainer confirmation, not in this fix)

MTVAL_WIDTH additionally carries an IDL requirement MXLEN == 32 -> MTVAL_WIDTH <= 32. The stval analogue would be SXLEN == 32 -> STVAL_WIDTH <= 32. I've left this out of the fix pending confirmation that SXLEN is available in the requirements.idl() evaluation context here (and that this constraint is wanted), to avoid an unverified IDL typecheck change — happy to add it in a follow-up.