Stacking attributes on interface instances

[keithpenney]

This relates to what my colleague @ldoolitt brought up in #294, I'm hoping to not drop the attributes added to an instance of an interface, but instead apply them to all the nets that make up the interface (and even stack them with any additional attributes. Here's an example input:

interface example_if (
  (* name="clk" *) input clk
);

(* name="gate" *)  wire gate;
(* name="data" *)  wire [7:0] data;

endinterface

module stack_attrs (
  input clk
);

(* hello=1 *) example_if example (
  .clk(clk)
);

endmodule

Current output:

module stack_attrs (clk);
	input clk;
	generate
		if (1) begin : example
			(* name = "clk" *) wire clk;
			(* name = "gate" *) wire gate;
			(* name = "data" *) wire [7:0] data;
		end
	endgenerate
	assign example.clk = clk;
endmodule

Desired output:

module stack_attrs (clk);
	input clk;
	generate
		if (1) begin : example
			(* hello = 1, name = "clk" *) wire clk;
			(* hello = 1, name = "gate" *) wire gate;
			(* hello = 1, name = "data" *) wire [7:0] data;
		end
	endgenerate
	assign example.clk = clk;
endmodule

I'm completely agnostic regarding whether this should be default behavior or enabled with a CLI argument, but it would be an enabling feature for my tool (which uses yosys in the back end) to support SV instead of just pure Verilog.

Does this seem doable?