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1. uart_tx_rtl uart_tx_rtl Public

   A parameterized and synthesizable UART Transmitter (TX) core in Verilog with a standard handshake interface.

   Verilog 2

2. axi4-lite-slave-verification axi4-lite-slave-verification Public

   SystemVerilog AXI4-Lite Slave IP with Hazard-Stalled FSM. Verified with 2M+ cycle randomized regression and 'Snoop & Serialize' collision handling.

   SystemVerilog 2

3. uart_rx_rtl uart_rx_rtl Public

   A robust, parameterizable UART Receiver (RX) designed in Verilog. Includes a flexible testbench for complete functional verification.

   Verilog 1

4. pwm_rtl pwm_rtl Public

   Parameterizable PWM Module in Verilog, Vivado

   Verilog

5. fifo_rtl fifo_rtl Public

   An robust Synchronous FIFO in Verilog RTL, featuring robust pointer-based logic for full/empty detection and support for simultaneous access.

   Verilog