v0.4.0

What's Changed

• feat: Add CXXRTL-based simulation infrastructure by @robtaylor in #161
• feat(rtl): support Verilog module parameters in RTLWrapper by @lanserge in #162
• feat(submit): pack design + pins.lock + manifest into a single bundle.zip by @lanserge in #165
• fix(auth): suggest 'gh auth refresh -s user:email' when token lacks the scope by @lanserge in #166
• feat(packaging): add BlockPackageDef for hard-macro builds by @lanserge in #167
• feat(packaging): add chipflow pin swap and chipflow pin show by @lanserge in #168
• feat(rtl): add load_blackbox_wrapper for NDA hard macros by @lanserge in #163

Full Changelog: v0.3.2...v0.4.0