A collection of RTL designs and digital circuits written in VHDL and Verilog.
This repository contains small learning projects for combinational logic, sequential logic, counters, display drivers, traffic-light control, LCD output, and VGA output. The projects are intended for study, simulation, and FPGA implementation with Xilinx Vivado.
Each project folder contains source files, testbenches, constraints, waveform captures, Vivado project files, or supporting documentation depending on the design. Start with the smaller modules, then move toward the full FPGA-style systems.
| Project | Description | Key Contents |
|---|---|---|
| Adders | Basic adder circuit implementations | Half adder, full adder, testbenches |
| FourBitAdder | 4-bit adder implementations | Behavioral and structural VHDL, waveforms |
| MUX | Multiplexer circuit design | 4-to-1 MUX and testbench |
| Decoders | Binary decoder circuit design | 2-to-4 decoder and testbench |
| AsyncRCntr | Asynchronous and up/down counter experiments | Ripple counter, push-button counter, BCD counter |
| PatternCounter | Pattern detection counter | Sequential logic design and testbench |
| Sequential | Sequential circuit examples | GCD ASM design and testbench |
| Two-Digit BCD Counter | Two-digit BCD counter design | Counter, seven-segment decoder, time mux |
| Traffic Light | Traffic light controller | ASM, countdown timer, waveform images |
| LCD display name | Simple LCD name display | LCD Verilog module and constraints |
| LCD Driver | LCD countdown timer project | LCD driver, timer, clock divider, constraints |
| LCDSlider | LCD slider/countdown timer files | LCD driver source and experiment PDF |
| VGA controller - Color display | VGA color output controller | VGA controller, clock divider, constraints, screenshot |
| VGA controller - Image Display | VGA image display controller | VGA controller, image memory IP, COE image data |
| VGA controller - Moving box | VGA Square display and controller | VGA controller, clock divider , BTN Debouncer, constraints |
- Open the project folder you want to study.
- Read the top-level module and identify the inputs, outputs, clocks, and reset signals.
- Run the available testbench or inspect the included waveform images.
- Open the Vivado project file when available to simulate, synthesize, or implement the design.
- Use LEARN.md for a suggested learning path through the repository.
- Xilinx Vivado - FPGA Synthesis and Implementation
- VHDL / Verilog - Hardware description languages used across the projects
See SECURITY.md for vulnerability reporting and safety notes.
See LICENSE for details.
Author: Darawsha Status: Computer Engineer