I am a M.Tech student running simulations in Verilog and Cadence. I spend my days navigating the delicate balance between RTL Design and "Will this simulation actually pass?" somehow, it usually does. When I'm not deep in Verilog or RISC-V architectures, I’m translating my aesthetic side into code using HTML, CSS. My code works on the first try about 0% of the time, but my coffee is always 100% cold.

• 🧩 Exploring the art (and science) of Design Verification
• 🔍 Learning SystemVerilog, UVM, and verification methodologies
• 🧠 Expanding my knowledge of Computer Architecture
• ⚡ Building and debugging RISC-V based hardware projects

• 🎯 Passionate about Digital Design, Verification, and Computer Architecture
• 🔬 Love analyzing waveforms, RTL logic, and simulation results
• 💬 Always excited to connect with people who enjoy chips, circuits, and coding
• 🎧 Powered by music, coffee, and late-night debugging sessions

• Designed components of a RISC-V processor using Verilog
• Implemented instruction decoding and datapath logic
• Simulated and verified functionality using ModelSim

⭐ Always in verification mode — both in code and in life.