MFCC core implementation in C (fixed point) and SystemVerilog with pipeline architecture.
This repository contains a complete implementation of an MFCC (Mel-Frequency Cepstral Coefficients) core, widely used in speech recognition and audio processing applications.
- C Implementation: Core developed using fixed-point arithmetic for improved performance in embedded systems with limited resources.
- SystemVerilog Implementation: IP with pipeline architecture, ideal for FPGA and ASIC synthesis, enabling high performance and parallelism.
Contributions are welcome! To collaborate on the development, please follow the guidelines outlined in the CONTRIBUTING.md file.
This project is licensed under the CERN-OHL-P-2.0, granting full freedom to use, modify, and redistribute.