verific: add -no_split_complex_ports option#5586
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dhvll wants to merge 3 commits intoYosysHQ:mainfrom
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Jan 5, 2026
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This should not be inside VERIFIC_SYSTEMVERILOG_SUPPORT, it is valid option in any case since it port bus can be generated in case of VHDL as well.
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This PR adds a new
verific -no_split_complex_portsoption that disables Verific’s default behavior of splitting complex ports during frontend elaboration.Silimate’s Yosys fork includes an option to disable this behavior explicitly.
Upstreaming this option allows users to control Verific’s port handling behavior while keeping the default behavior unchanged.
The change introduces a boolean
verific_no_split_complex_portsflag that is set when the-no_split_complex_portsoption is passed to theverificfrontend.When enabled, the flag disables Verific’s complex port splitting behavior during elaboration. The implementation is guarded under
VERIFIC_SYSTEMVERILOG_SUPPORTand does not affect existing behavior unless the option is explicitly used.