High-sampling-rate, high-memory-density, multi-channel arbitrary waveform generator. Waveforms are transferred from PS to PL via AXI DMA, stored in RAM, and streamed to the on-chip DACs.
- Data sampling at 9.8304 GSps
- Two output channels: DAC A (DAC0) and DAC B (DAC2)
- Four waveforms total, each
$2^{18}$ samples- DAC A (DAC0): waveform A or B
- DAC B (DAC2): waveform C or D
- Waveform selection via software (AXI GPIO) or an external signal.
- Sample loading within 5-7 ms.
The implementation is summarized with the help of the following diagrams. It is separated into the waveform-write and the waveform-read blocks.
The sample comprising the waveforms A,B,C, and D are fed into the PL via an AXI-DMA with samples in the sequence shown in the diagram. The stream then passes through a Data Sorter module, which reorders the incoming samples and writes them into the RAM banks using the memory layout depicted in the diagram. During this process, the write_enable signal is held high.
For the memory block RAM[0] and RAM[1], the first
On the read side, the address counter increments with a clock signal clk0 for RAM[0],and RAM[1]) and with clk2 for RAM[2], and RAM[3]). Both clocks operate at 614.4 MHz - 16x slower than the DAC sampling rate.
At each rising edge of clk0, the 16 samples - 8 samples on RAM[0], and 8 samples on RAM[1] at the same address counter - are concatenated and sent to the DAC IP for output on DAC0 (DAC A). When the waveform select signal : (control_trigger || axi_control) is high, an offset of
| Input | Output |
|---|---|
 |
 |
The relevant I/O pins and ports on the board are
| Name | Pin/Port | Type | Description |
|---|---|---|---|
| control_trigger | PMOD0_1 | Input | External waveform-select trigger. Toggles DAC A between waveform-A/waveform-B and DAC B between waveform-C/waveform-D. Effective select: (axi_control |
| pmod_out | PMOD0_0 | Output | Outputs control_trigger signal sampled on a 614.4 MHz clock. |
| DAC 0 | DAC A | Output | AWG output |
| DAC 2 | DAC B | Output | AWG output |
The design contains AXI GPIOs that can be accessed by software. A sample C code is provided.
| Name | Memory Address | Type | Description |
|---|---|---|---|
| rst_n | 0x00_A007_0000 | Output | 1 bit. Software reset. Active low signal. |
| write_enable | 0x00_A005_0000 | Output | 1 bit. Enables writing waveform to RAM bank. Set to 0 to enable output; set enable_ch0 and enambe_ch2 accordingly. |
| MAX_POINTS | 0x00_A006_0000 | Output | 32 bit. (MAX_POINTS<<4) is the maximum number of points to output. |
| enable_ch0 | 0x00_A009_0000 | Output | 1 bit. Enables output on DAC A when write_enable is low. |
| enable_ch2 | 0x00_A00A_0000 | Output | 1 bit. Enables output on DAC B when write_enable is low. |
| axi_control | 0x00_A008_0000 | Output | 1 bit. Software trigger signal. Switches between waveform-A and waveform-B for DAC0 output and between waveform-C and waveform-D for DAC2 output. The effective select signal is (axi_control |
| axi_dma_0 | 0x00_A006_0000 | Input | AMD's DMA IP for direct memory access and fast transfer of data from PS to PL. |
A sample jupyter notebook file is provided.
- Copy the .ipynb, the LMK and the LMX files, the .hwh file into the same folder in the device.
- Extract the .7z file to obtain the .bit file at the same location.
- Run the notebook from within the Linux OS on the FPGA.
The project can be built as a Vivado project using the awg_multichannel_rfsoc.tcl and necessary modifications can be made. The board file can be installed from https://github.com/RealDigitalOrg/RFSoC4x2-BSP