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[BUG] `$fatal` call in `cve2_top_tracing.sv` not following latest SystemVerilog IEEE standard (1800-2012)

good first issue

#321

· ozografos opened

on Mar 10, 2026

[BUG] cve2_riscv_compliance simulator fails to load any ELF/vmem

#319

· karabambus opened

on Mar 9, 2026

Build fails with Verilator 5.x due to missing warning suppressions

#318

· karabambus opened

on Mar 9, 2026

Should the CVE2 fence instruction should wait for xif scoreboard?

#317

· ClementChone opened

on Mar 6, 2026

[BUG] cv32e20 fails to raise issue_valid on X-IF for coprocessor CSR instructions

#316

· anecorral opened

on Feb 25, 2026

[BUG] Core lockup with short debug pulses (1-2 cycles)

#314

· Amit-Matth opened

on Feb 19, 2026

[TASK] Incorporate Architectural Compliance Tests (ACT4.0) into a CVE2 testbench

#303

· MikeOpenHWGroup opened

on Nov 3, 2025

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[TASK] Add RVFI specification to Reference Guide

#299

· MikeOpenHWGroup opened

on Oct 6, 2025

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[TASK] Update "core" files for FuseSoC

good first issue

#298

· MikeOpenHWGroup opened

on Oct 4, 2025

[TASK] Update Section 3 of the User Manual to drop retired features

#281

· MikeOpenHWGroup opened

on Feb 18, 2025

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[TASK] Clean-up documentation to align with CVE2 Project Concept

#280

· MikeOpenHWGroup opened

on Feb 18, 2025

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Should the CV32E20 update the target ISA Specifications?

#274

· MikeOpenHWGroup opened

on Jun 7, 2024