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2 followers · 4 following
  • M.Tech (SPDD) - DTU'26
  • New Delhi
  • 00:14 (UTC +05:30)
  • LinkedIn in/shubham3279

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shubham3279/README.md

Hi 👋! I am Shubham.

Product Validation Engineer II at Cadence Design Systems
DFT (ATPG) domain · Modus

M.Tech. ECE — Signal Processing & Digital Design
Delhi Technological University

Interests: semiconductor technology, computer architecture, and hardware-software co-design for AI/ML systems.

⚙️ Tech & Tools

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  1. accelerated-architectures accelerated-architectures Public

  2. cs-fundamentals cs-fundamentals Public

  3. design-for-test design-for-test Public

  4. soft-intelligence soft-intelligence Public