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Generate decoder from ISA descriptor#725

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yc199911 wants to merge 1 commit intosysprog21:masterfrom
yc199911:issue-103-decoder-gen
Open

Generate decoder from ISA descriptor#725
yc199911 wants to merge 1 commit intosysprog21:masterfrom
yc199911:issue-103-decoder-gen

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@yc199911 yc199911 commented Apr 9, 2026

Summary

Introduce scripts/gen-decoder.py to automatically generate
src/decode.c from src/instructions.in, replacing the hand-written
decoder.

Changes

  • src/instructions.in: ISA descriptor for 161 instructions
  • scripts/gen-decoder.py: decision-tree builder and C code generator
  • scripts/verify-tree.py: validates all instructions are reachable
  • Makefile: auto-regenerate decode.c when inputs change
  • docs/decoder-generator.md: format documentation

Test Results

RISCV_DEVICE=IMACFZicsrZifencei: all tests passed
(I, M, A, F, C, Zifencei, privilege extensions verified)

Close #103


Summary by cubic

Replaced the hand-written instruction decoder with an auto-generated one built from an ISA descriptor. This makes adding instructions simple and keeps decoding consistent and verifiable across 161 ops.

  • New Features

    • scripts/gen-decoder.py builds a decision tree and emits src/decode.c (includes full RVC operand decoding and extension guards).
    • scripts/verify-tree.py validates reachability for every instruction (current descriptor: 161/161).
    • src/instructions.in defines the ISA; docs/decoder-generator.md documents the format and how to extend it.
    • Makefile rule auto-regenerates src/decode.c and runs clang-format.
  • Migration

    • No runtime changes; src/decode.c stays committed for normal builds.
    • To add an instruction: edit src/instructions.in and run make. For new RVC immediates, add a decoder in _RVC_OPERAND_DECODERS in scripts/gen-decoder.py.

Written for commit 8ef6e5d. Summary will update on new commits.

Introduce gen-decoder.py that reads src/instructions.in and generates
src/decode.c, replacing the hand-written decoder with an auto-generated
one.

- src/instructions.in: ISA descriptor covering 161 instructions
  (RV32I/M/A/F/C, Zifencei, Zicsr, Zba/Zbb/Zbc/Zbs)
- scripts/gen-decoder.py: decision-tree builder and C code generator
  with full RVC operand decoding (register mapping + immediate
  bit-extraction)
- scripts/verify-tree.py: validates all 161 instructions are reachable
  in the generated decision tree
- Makefile: auto-regenerate decode.c when inputs change
- docs/decoder-generator.md: describes the descriptor format and how
  to add new instructions/extensions

Close sysprog21#103
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Benchmarks

Details
Benchmark suite Current: 8ef6e5d Previous: 2138efe Ratio
Dhrystone 1521.667 DMIPS 1558.667 DMIPS 1.02
CoreMark 1103.066 iterations/sec 1103.567 iterations/sec 1.00

This comment was automatically generated by workflow using github-action-benchmark.

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Generate RISC-V instruction decoder from ISA descriptor

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