quartic-rtl2gds

RTL to GDSII implementation of Y = 4ˣ on SAED 32nm RVT standard cells using Synopsys VLSI toolchain.

1. Overview

• Function: Y = 4^X, where X is a 2-bit unsigned integer (outputs: 1, 4, 16, 64)
• Implementation: Two-stage pipeline — input register followed by a barrel shift to compute 4^X
• PDK: SAED 32nm RVT (saed32rvt_tt0p78vn40c)
• Target clock: 500 MHz (2 ns period)
• Flow: VCS/Verdi → Design Compiler → IC Compiler II → PrimeTime

2. Results

Metric	Value
Clock Frequency	500 MHz
Setup Slack (WNS, post-route)	1.62 ns
Cell Area	50.32 μm²
Total Area (with interconnect)	52.94 μm²
Total Power (ICC2, post-route)	0.139 mW
Dynamic Power (DC synthesis)	11.54 μW
Routed Wire Length	98 μm
DRC Violations	0
STA Violations (both corners)	0

3. RTL

// pow4.v — Y = 4^X, X is 2-bit unsigned
module pow4 (
    input  wire       clk,
    input  wire [1:0] X,
    output reg  [6:0] Y
);
    reg [1:0] X_reg;
    always @(posedge clk) X_reg <= X;
    always @(posedge clk) Y <= 7'd1 << ({1'b0, X_reg} << 1);
endmodule

Simulation

All 4 test cases pass (fail_cnt = 0).

GTKWave: X = 00, 01, 10, 11 → Y = 01, 04, 10, 40 (hex)

4. Logic Synthesis

Tool: Synopsys Design Compiler
Library: saed32rvt_tt0p78vn40c.db
Constraints: 2 ns clock period, 0.1 ns setup / 0.05 ns hold uncertainty, 0.2 ns I/O delays
Note: AND cells set to dont_use to steer synthesis toward NOR/NAND/INV primitives.

5. Physical Design

Tool: IC Compiler II

Floorplan

L-shaped die (side_length {8 8 4 4 8 8}), 0.5 μm core offset. X/Y ports constrained to side 6, clock to side 2.

Parameter	Value
Setup WNS	1.62 ns
Routing Violations	None
Cell Area	50.32 μm²

Power Planning

PG ring on M7/M8 (0.4 μm width, 0.3 μm spacing). Mesh on M6/M7/M8 at 5 μm pitch with interleaving spacing. Standard-cell rails on M1 (0.06 μm width).

Placement

AND cells retained as dont_use consistent with synthesis. Zero legality violations post-placement.

Parameter	Value
Setup WNS	1.62 ns
Hold WNS	0.06 ns
Legality Violations	0
Connectivity	Fully connected

Clock Tree Synthesis

6 clock sinks. No repeaters inserted. Global skew: 0.00 ns, max latency: 0.00 ns.

Routing

No open nets. No DRC violations. Total routed wire length: 98 μm.

6. Static Timing Analysis

Tool: Synopsys PrimeTime
Parasitics back-annotated from SPEF at 125°C (late and early corners).

Corner	Library	Setup	Hold
Late (Cmax / SS)	saed32rvt_ss0p7vn40c.db	0 violations	0 violations
Early (Cmin / FF)	saed32rvt_ff1p16v125c.db	0 violations	0 violations

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Check out the report here.