Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
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Updated
Feb 13, 2025 - VHDL
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
8x seven-segment display peripheral board for the TRIPI (Trion-based FPGA) platform with buttons, switches and reset
VLSI-Based Digital Clock with Alarm Functionality using Verilog HDL featuring HH:MM:SS timekeeping, alarm control, snooze logic, 12/24-hour mode, seven-segment display support, simulation, waveform verification, and FPGA-ready architecture.
Laboratory exercises for the course CAD for Digital Hardware (E-CAD), covering graphical digital design, PCB back-end flow, and HDL-based FPGA implementation using VHDL, ModelSim, and Vivado on the Basys3 (Artix-7) board.
Practical study guide for Verilog, C and Python using an ALU as the central project, with digital hardware concepts, reference models, and automated verification.
Create harmonium sounds by pressing keys while controlling air pressure through your laptop’s lid angle with a Python-powered web app.
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