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digitalsystemdesign

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Structural Verilog implementation of an IEEE 754 single-precision floating-point (FP32) datapath for Multi-Layer Perceptron (MLP) neural network inference. This repository decomposes a sigmoid neuron into modular floating-point arithmetic IP units, culminating in a 4-element streaming vector dot-product engine cascaded into an activation pipeline.

  • Updated Aug 27, 2026
  • Verilog

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