Lab solutions of MIT Manipal CSE Dept. for Batch of 2024.
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Updated
Apr 11, 2024 - C
Lab solutions of MIT Manipal CSE Dept. for Batch of 2024.
Most of the slides and exercises are my projects and manuscripts (★‿★)
Digital clock & customizable alarm system
Date of Respository Creation: 05/08/2023. This project was undertaken as a part of 4th semester System Verilog Project.
DIGITAL CIRCUIT SIMULATOR - an OBJECT ORIENTED PROGRAMMING way of implemeting LOGIC GATES ICs
Projects I made in Digital System Lab. I used Logisim for my projects.
A Morse code encoder system implemented on FPGA
A collection of projects and materials related to digital system design.
Learned as a part of CS210 course
Structural Verilog implementation of an IEEE 754 single-precision floating-point (FP32) datapath for Multi-Layer Perceptron (MLP) neural network inference. This repository decomposes a sigmoid neuron into modular floating-point arithmetic IP units, culminating in a 4-element streaming vector dot-product engine cascaded into an activation pipeline.
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