Code and circuits — both help me think clearly when the world gets noisy.
I use this space to build and document real RTL and FPGA projects — from simulation to on-board hardware deployment.
If you're interested in Verilog, VHDL, FPGA design, or hardware-aware signal processing, you'll feel at home here.
- M.Tech student at IIT Roorkee, specializing in Advanced Instrumentation & Artificial Intelligence
- Several FPGA projects deployed on ZedBoard and Spartan-3E hardware
- Research trained at NTHU Taiwan and IIT Hyderabad in semiconductor fabrication & technology
- GATE EC 2025 & EC 2024 Qualified
- Exploring hardware–algorithm co-design, where signal processing and RTL design meet silicon
| Project | Language | Board | Status |
|---|---|---|---|
| UART Communication System | VHDL | Spartan-3E | ✅ Complete |
| Electronic Voting Machine | VHDL | ZedBoard | ✅ Complete |
| FPGA-Based Real-Time Sliding Discrete Fourier Transform (SDFT) Implementation | Verilog | FPGA | 🔧 In Progress |
| 16-bit RISC-V CPU | Verilog | Zedboard/Spartan-3E | 🔧 In Progress |
C / C++ | Embedded C | Verilog | VHDL | MATLAB | Python | 8085 Assembly
Digital Electronics | Analog & Digital Circuits | Semiconductor Devices | Microprocessors & Microcontrollers | FPGA-based Digital System Design | Static Timing Analysis
Xilinx Vivado | Xilinx ISE | GTKWave | Proteus | LTSpice / PSpice | Arduino IDE
RTL Design & Timing Closure | FPGA-based DSP | Sliding DFT & Filter Design | Signal Processing | Sensors & Instrumentation | Hardware-Aware AI
- 🔧 FPGA-Based Real-Time Sliding Discrete Fourier Transform (SDFT) Implementation — Verilog, Intel Quartus, MATLAB Simulink, DSP Builder, FPGA Deployment
- 🖥️ 16-bit pipelined RISC-V CPU — Verilog, RV32I ISA, FPGA Deployment (Zedboard/Spartan 3E)
- 📐 M.Tech Thesis — FPGA Realization of the Observer-Based Sliding Discrete Fourier Transform
I'm open to feedback, suggestions, and optimization ideas — feel free to explore, raise issues, or share insights.