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[verilator] Add waiver to control signals that Verilator warns of 'cicular combinational logic', but that are expected.#320

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davideschiavone merged 1 commit intoopenhwgroup:mainfrom
cairo-caplan:waiver_unopt
Mar 10, 2026
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Verilator 5.042+ warns that some of the CVE2 control signals could be combinational loop, emitting the warning messages below when running the make lint-top-tracing target for example.

Those signals are not combinational loops as they would be detected on other tests, as they would be unstable.
This issue was also reported recently on the IBEX project ( #2345 and #2355 ).

I found it out while reviewing and reproducing locally PR #315, but finally it should also address issue #318, which depends on Verilator to build a simulation model.

ERROR: %Warning-UNOPTFLAT: ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_id_stage.sv:199:16: Signal unoptimizable: Circular combinational logic: 'cve2_top_tracing.u_cve2_top.u_cve2_core.id_stage_i.instr_executing_spec'
  199 |   logic        instr_executing_spec;
      |                ^~~~~~~~~~~~~~~~~~~~
                    ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=5.045
                    ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_id_stage.sv:199:16:      Example path: cve2_top_tracing.u_cve2_top.u_cve2_core.id_stage_i.instr_executing_spec
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_id_stage.sv:778:3:      Example path: ALWAYS
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_id_stage.sv:247:16:      Example path: cve2_top_tracing.u_cve2_top.u_cve2_core.id_stage_i.stall_alu
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_id_stage.sv:898:19:      Example path: ASSIGNW
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_id_stage.sv:207:16:      Example path: cve2_top_tracing.u_cve2_top.u_cve2_core.id_stage_i.stall_id
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_controller.sv:321:3:      Example path: ALWAYS
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_controller.sv:130:9:      Example path: cve2_top_tracing.u_cve2_top.u_cve2_core.id_stage_i.controller_i.halt_if
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_controller.sv:722:24:      Example path: ASSIGNW
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_core.sv:234:16:      Example path: cve2_top_tracing.u_cve2_top.u_cve2_core.id_in_ready
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_controller.sv:321:3:      Example path: ALWAYS
%Warning-UNOPTFLAT: ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_core.sv:234:16: Signal unoptimizable: Circular combinational logic: 'cve2_top_tracing.u_cve2_top.u_cve2_core.id_in_ready'
  234 |   logic        id_in_ready;
      |                ^~~~~~~~~~~
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_core.sv:234:16:      Example path: cve2_top_tracing.u_cve2_top.u_cve2_core.id_in_ready
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_controller.sv:321:3:      Example path: ALWAYS
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_controller.sv:130:9:      Example path: cve2_top_tracing.u_cve2_top.u_cve2_core.id_stage_i.controller_i.halt_if
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_controller.sv:722:24:      Example path: ASSIGNW
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_core.sv:234:16:      Example path: cve2_top_tracing.u_cve2_top.u_cve2_core.id_in_ready
%Warning-UNOPTFLAT: ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_core.sv:245:16: Signal unoptimizable: Circular combinational logic: 'cve2_top_tracing.u_cve2_top.u_cve2_core.en_wb'
  245 |   logic        en_wb;
      |                ^~~~~
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_core.sv:245:16:      Example path: cve2_top_tracing.u_cve2_top.u_cve2_core.en_wb
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_id_stage.sv:715:34:      Example path: ASSIGNW
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_core.sv:218:16:      Example path: cve2_top_tracing.u_cve2_top.u_cve2_core.csr_op_en
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_controller.sv:226:22:      Example path: ASSIGNW
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_controller.sv:136:9:      Example path: cve2_top_tracing.u_cve2_top.u_cve2_core.id_stage_i.controller_i.special_req
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_controller.sv:321:3:      Example path: ALWAYS
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_controller.sv:130:9:      Example path: cve2_top_tracing.u_cve2_top.u_cve2_core.id_stage_i.controller_i.halt_if
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_controller.sv:722:24:      Example path: ASSIGNW
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_core.sv:234:16:      Example path: cve2_top_tracing.u_cve2_top.u_cve2_core.id_in_ready
                    ../src/openhwgroup_cve2_cve2_core_0.1/rtl/cve2_controller.sv:321:3:      Example path: ALWAYS
%Error: Exiting due to 3 warning(s)
make[1]: *** [Makefile:16: Vcve2_top_tracing.mk] Error 1

…rcular combinational logic', but that are expected.
@cairo-caplan
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@davideschiavone , can I ask you to have a look on that :)

@davideschiavone davideschiavone merged commit d7b6132 into openhwgroup:main Mar 10, 2026
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