[verilator] Add waiver to control signals that Verilator warns of 'cicular combinational logic', but that are expected.#320
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davideschiavone merged 1 commit intoopenhwgroup:mainfrom Mar 10, 2026
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…rcular combinational logic', but that are expected.
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@davideschiavone , can I ask you to have a look on that :) |
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Verilator 5.042+ warns that some of the CVE2 control signals could be combinational loop, emitting the warning messages below when running the
make lint-top-tracingtarget for example.Those signals are not combinational loops as they would be detected on other tests, as they would be unstable.
This issue was also reported recently on the IBEX project ( #2345 and #2355 ).
I found it out while reviewing and reproducing locally PR #315, but finally it should also address issue #318, which depends on Verilator to build a simulation model.